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-rw-r--r--include/hw/arm/aspeed.h3
-rw-r--r--include/hw/arm/aspeed_coprocessor.h61
-rw-r--r--include/hw/arm/aspeed_soc.h61
-rw-r--r--include/hw/arm/boot.h3
-rw-r--r--include/hw/arm/fsl-imx25.h2
-rw-r--r--include/hw/arm/fsl-imx31.h2
-rw-r--r--include/hw/arm/fsl-imx6.h2
-rw-r--r--include/hw/arm/fsl-imx6ul.h2
-rw-r--r--include/hw/arm/max78000_soc.h50
-rw-r--r--include/hw/arm/npcm8xx.h7
-rw-r--r--include/hw/arm/omap.h538
-rw-r--r--include/hw/arm/sharpsl.h17
-rw-r--r--include/hw/arm/smmu-common.h1
-rw-r--r--include/hw/arm/soc_dma.h4
-rw-r--r--include/hw/arm/stm32f205_soc.h2
-rw-r--r--include/hw/arm/stm32l4x5_soc.h2
-rw-r--r--include/hw/arm/virt.h14
-rw-r--r--include/hw/arm/xen_arch_hvm.h9
-rw-r--r--include/hw/arm/xlnx-versal-version.h16
-rw-r--r--include/hw/arm/xlnx-versal.h342
-rw-r--r--include/hw/arm/xlnx-zynqmp.h5
21 files changed, 525 insertions, 618 deletions
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 9cae45a..6c36455 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -35,11 +35,14 @@ struct AspeedMachineClass {
uint32_t hw_strap2;
const char *fmc_model;
const char *spi_model;
+ const char *spi2_model;
uint32_t num_cs;
+ uint32_t num_cs2;
uint32_t macs_mask;
void (*i2c_init)(AspeedMachineState *bmc);
uint32_t uart_default;
bool sdhci_wp_inverted;
+ bool vbootrom;
};
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
new file mode 100644
index 0000000..d77655d
--- /dev/null
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -0,0 +1,61 @@
+/*
+ * ASPEED Coprocessor
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_COPROCESSOR_H
+#define ASPEED_COPROCESSOR_H
+
+#include "qom/object.h"
+#include "hw/arm/aspeed_soc.h"
+
+struct AspeedCoprocessorState {
+ DeviceState parent;
+
+ MemoryRegion *memory;
+ MemoryRegion sram;
+ Clock *sysclk;
+
+ AspeedSCUState scu;
+ AspeedSCUState scuio;
+ AspeedTimerCtrlState timerctrl;
+ SerialMM uart[ASPEED_UARTS_NUM];
+};
+
+#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
+OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
+ ASPEED_COPROCESSOR)
+
+struct AspeedCoprocessorClass {
+ DeviceClass parent_class;
+
+ /** valid_cpu_types: NULL terminated array of a single CPU type. */
+ const char * const *valid_cpu_types;
+ uint32_t silicon_rev;
+ const hwaddr *memmap;
+ const int *irqmap;
+ int uarts_base;
+ int uarts_num;
+};
+
+struct Aspeed27x0CoprocessorState {
+ AspeedCoprocessorState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
+ ASPEED27X0SSP_COPROCESSOR)
+
+#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
+DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
+ ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCESSOR)
+
+#endif /* ASPEED_COPROCESSOR_H */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f069d17..4b8e599 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -37,18 +37,22 @@
#include "qom/object.h"
#include "hw/misc/aspeed_lpc.h"
#include "hw/misc/unimp.h"
+#include "hw/pci-host/aspeed_pcie.h"
#include "hw/misc/aspeed_peci.h"
#include "hw/fsi/aspeed_apb2opb.h"
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
+#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
+
#define ASPEED_SPIS_NUM 3
-#define ASPEED_EHCIS_NUM 2
+#define ASPEED_EHCIS_NUM 4
#define ASPEED_WDTS_NUM 8
#define ASPEED_CPUS_NUM 4
#define ASPEED_MACS_NUM 4
#define ASPEED_UARTS_NUM 13
#define ASPEED_JTAG_NUM 2
+#define ASPEED_PCIE_NUM 3
struct AspeedSoCState {
DeviceState parent;
@@ -59,6 +63,8 @@ struct AspeedSoCState {
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
+ MemoryRegion vbootrom;
+ MemoryRegion pcie_mmio_alias[ASPEED_PCIE_NUM];
AddressSpace dram_as;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
@@ -86,10 +92,14 @@ struct AspeedSoCState {
AspeedSDHCIState sdhci;
AspeedSDHCIState emmc;
AspeedLPCState lpc;
+ AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
+ AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
AspeedPECIState peci;
SerialMM uart[ASPEED_UARTS_NUM];
Clock *sysclk;
UnimplementedDeviceState iomem;
+ UnimplementedDeviceState iomem0;
+ UnimplementedDeviceState iomem1;
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
@@ -97,6 +107,7 @@ struct AspeedSoCState {
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState sgpiom;
+ UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
};
@@ -153,6 +164,7 @@ struct AspeedSoCClass {
uint32_t silicon_rev;
uint64_t sram_size;
uint64_t secsram_size;
+ int pcie_num;
int spis_num;
int ehcis_num;
int wdts_num;
@@ -162,15 +174,16 @@ struct AspeedSoCClass {
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
- qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
bool (*boot_from_emmc)(AspeedSoCState *s);
};
-const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
-
enum {
+ ASPEED_DEV_VBOOTROM,
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
+ ASPEED_DEV_IOMEM0,
+ ASPEED_DEV_IOMEM1,
+ ASPEED_DEV_LTPI,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@@ -192,6 +205,8 @@ enum {
ASPEED_DEV_SPI2,
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
+ ASPEED_DEV_EHCI3,
+ ASPEED_DEV_EHCI4,
ASPEED_DEV_VIC,
ASPEED_DEV_INTC,
ASPEED_DEV_INTCIO,
@@ -220,6 +235,15 @@ enum {
ASPEED_DEV_LPC,
ASPEED_DEV_IBT,
ASPEED_DEV_I2C,
+ ASPEED_DEV_PCIE0,
+ ASPEED_DEV_PCIE1,
+ ASPEED_DEV_PCIE2,
+ ASPEED_DEV_PCIE_PHY0,
+ ASPEED_DEV_PCIE_PHY1,
+ ASPEED_DEV_PCIE_PHY2,
+ ASPEED_DEV_PCIE_MMIO0,
+ ASPEED_DEV_PCIE_MMIO1,
+ ASPEED_DEV_PCIE_MMIO2,
ASPEED_DEV_PECI,
ASPEED_DEV_ETH1,
ASPEED_DEV_ETH2,
@@ -249,32 +273,43 @@ enum {
ASPEED_DEV_SLIIO,
ASPEED_GIC_DIST,
ASPEED_GIC_REDIST,
+ ASPEED_DEV_IPC0,
+ ASPEED_DEV_IPC1,
};
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
+const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
+bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
+ const hwaddr addr, Error **errp);
+void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
+ int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
+ hwaddr addr);
+void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
const char *name, hwaddr addr,
uint64_t size);
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
unsigned int count, int unit0);
+void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
+ Error **errp);
+void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
+ MemoryRegion *boot_rom, uint64_t rom_size);
+void aspeed_load_vbootrom(AspeedSoCState *soc, const char *bios_name,
+ Error **errp);
static inline int aspeed_uart_index(int uart_dev)
{
return uart_dev - ASPEED_DEV_UART0;
}
-static inline int aspeed_uart_first(AspeedSoCClass *sc)
+static inline int aspeed_uart_first(int uarts_base)
{
- return aspeed_uart_index(sc->uarts_base);
+ return aspeed_uart_index(uarts_base);
}
-static inline int aspeed_uart_last(AspeedSoCClass *sc)
+static inline int aspeed_uart_last(int uarts_base, int uarts_num)
{
- return aspeed_uart_first(sc) + sc->uarts_num - 1;
+ return aspeed_uart_first(uarts_base) + uarts_num - 1;
}
#endif /* ASPEED_SOC_H */
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index b12bf61..a2e22bd 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -132,6 +132,9 @@ struct arm_boot_info {
bool secure_board_setup;
arm_endianness endianness;
+
+ /* CPU having load the kernel and that should be the first to boot. */
+ ARMCPU *primary_cpu;
};
/**
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index df2f839..b68d433 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -29,7 +29,7 @@
#include "hw/sd/sdhci.h"
#include "hw/usb/chipidea.h"
#include "hw/watchdog/wdt_imx2.h"
-#include "exec/memory.h"
+#include "system/memory.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index 40c593a..41232a2 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -25,7 +25,7 @@
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
#include "hw/watchdog/wdt_imx2.h"
-#include "exec/memory.h"
+#include "system/memory.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 9da32fc..124bbd4 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -34,7 +34,7 @@
#include "hw/usb/imx-usb-phy.h"
#include "hw/pci-host/designware.h"
#include "hw/or-irq.h"
-#include "exec/memory.h"
+#include "system/memory.h"
#include "cpu.h"
#include "qom/object.h"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 8277b0e..4e3209b 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -33,7 +33,7 @@
#include "hw/net/imx_fec.h"
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
-#include "exec/memory.h"
+#include "system/memory.h"
#include "cpu.h"
#include "qom/object.h"
#include "qemu/units.h"
diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h
new file mode 100644
index 0000000..a203079
--- /dev/null
+++ b/include/hw/arm/max78000_soc.h
@@ -0,0 +1,50 @@
+/*
+ * MAX78000 SOC
+ *
+ * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_ARM_MAX78000_SOC_H
+#define HW_ARM_MAX78000_SOC_H
+
+#include "hw/or-irq.h"
+#include "hw/arm/armv7m.h"
+#include "hw/misc/max78000_aes.h"
+#include "hw/misc/max78000_gcr.h"
+#include "hw/misc/max78000_icc.h"
+#include "hw/char/max78000_uart.h"
+#include "hw/misc/max78000_trng.h"
+#include "qom/object.h"
+
+#define TYPE_MAX78000_SOC "max78000-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC)
+
+#define FLASH_BASE_ADDRESS 0x10000000
+#define FLASH_SIZE (512 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (128 * 1024)
+
+/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */
+#define MAX78000_NUM_ICC 2
+#define MAX78000_NUM_UART 3
+
+struct MAX78000State {
+ SysBusDevice parent_obj;
+
+ ARMv7MState armv7m;
+
+ MemoryRegion sram;
+ MemoryRegion flash;
+
+ Max78000GcrState gcr;
+ Max78000IccState icc[MAX78000_NUM_ICC];
+ Max78000UartState uart[MAX78000_NUM_UART];
+ Max78000TrngState trng;
+ Max78000AesState aes;
+
+ Clock *sysclk;
+};
+
+#endif
diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h
index 9812e6f..a8377db 100644
--- a/include/hw/arm/npcm8xx.h
+++ b/include/hw/arm/npcm8xx.h
@@ -28,7 +28,8 @@
#include "hw/misc/npcm7xx_mft.h"
#include "hw/misc/npcm7xx_pwm.h"
#include "hw/misc/npcm7xx_rng.h"
-#include "hw/net/npcm7xx_emc.h"
+#include "hw/net/npcm_gmac.h"
+#include "hw/net/npcm_pcs.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/sd/npcm7xx_sdhci.h"
#include "hw/timer/npcm7xx_timer.h"
@@ -36,6 +37,7 @@
#include "hw/usb/hcd-ehci.h"
#include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h"
+#include "hw/ssi/npcm_pspi.h"
#define NPCM8XX_MAX_NUM_CPUS (4)
@@ -98,7 +100,10 @@ struct NPCM8xxState {
EHCISysBusState ehci[2];
OHCISysBusState ohci[2];
NPCM7xxFIUState fiu[3];
+ NPCMGMACState gmac[4];
+ NPCMPCSState pcs;
NPCM7xxSDHCIState mmc;
+ NPCMPSPIState pspi;
};
struct NPCM8xxClass {
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 7cb87ea..bdb2e88 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -20,29 +20,29 @@
#ifndef HW_ARM_OMAP_H
#define HW_ARM_OMAP_H
-#include "exec/memory.h"
+#include "system/memory.h"
#include "target/arm/cpu-qom.h"
#include "qemu/log.h"
#include "qom/object.h"
-# define OMAP_EMIFS_BASE 0x00000000
-# define OMAP_CS0_BASE 0x00000000
-# define OMAP_CS1_BASE 0x04000000
-# define OMAP_CS2_BASE 0x08000000
-# define OMAP_CS3_BASE 0x0c000000
-# define OMAP_EMIFF_BASE 0x10000000
-# define OMAP_IMIF_BASE 0x20000000
-# define OMAP_LOCALBUS_BASE 0x30000000
-# define OMAP_MPUI_BASE 0xe1000000
-
-# define OMAP730_SRAM_SIZE 0x00032000
-# define OMAP15XX_SRAM_SIZE 0x00030000
-# define OMAP16XX_SRAM_SIZE 0x00004000
-# define OMAP1611_SRAM_SIZE 0x0003e800
-# define OMAP_CS0_SIZE 0x04000000
-# define OMAP_CS1_SIZE 0x04000000
-# define OMAP_CS2_SIZE 0x04000000
-# define OMAP_CS3_SIZE 0x04000000
+#define OMAP_EMIFS_BASE 0x00000000
+#define OMAP_CS0_BASE 0x00000000
+#define OMAP_CS1_BASE 0x04000000
+#define OMAP_CS2_BASE 0x08000000
+#define OMAP_CS3_BASE 0x0c000000
+#define OMAP_EMIFF_BASE 0x10000000
+#define OMAP_IMIF_BASE 0x20000000
+#define OMAP_LOCALBUS_BASE 0x30000000
+#define OMAP_MPUI_BASE 0xe1000000
+
+#define OMAP730_SRAM_SIZE 0x00032000
+#define OMAP15XX_SRAM_SIZE 0x00030000
+#define OMAP16XX_SRAM_SIZE 0x00004000
+#define OMAP1611_SRAM_SIZE 0x0003e800
+#define OMAP_CS0_SIZE 0x04000000
+#define OMAP_CS1_SIZE 0x04000000
+#define OMAP_CS2_SIZE 0x04000000
+#define OMAP_CS3_SIZE 0x04000000
/* omap_clk.c */
struct omap_mpu_state_s;
@@ -103,228 +103,228 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
* Common IRQ numbers for level 1 interrupt handler
* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
*/
-# define OMAP_INT_CAMERA 1
-# define OMAP_INT_FIQ 3
-# define OMAP_INT_RTDX 6
-# define OMAP_INT_DSP_MMU_ABORT 7
-# define OMAP_INT_HOST 8
-# define OMAP_INT_ABORT 9
-# define OMAP_INT_BRIDGE_PRIV 13
-# define OMAP_INT_GPIO_BANK1 14
-# define OMAP_INT_UART3 15
-# define OMAP_INT_TIMER3 16
-# define OMAP_INT_DMA_CH0_6 19
-# define OMAP_INT_DMA_CH1_7 20
-# define OMAP_INT_DMA_CH2_8 21
-# define OMAP_INT_DMA_CH3 22
-# define OMAP_INT_DMA_CH4 23
-# define OMAP_INT_DMA_CH5 24
-# define OMAP_INT_DMA_LCD 25
-# define OMAP_INT_TIMER1 26
-# define OMAP_INT_WD_TIMER 27
-# define OMAP_INT_BRIDGE_PUB 28
-# define OMAP_INT_TIMER2 30
-# define OMAP_INT_LCD_CTRL 31
+#define OMAP_INT_CAMERA 1
+#define OMAP_INT_FIQ 3
+#define OMAP_INT_RTDX 6
+#define OMAP_INT_DSP_MMU_ABORT 7
+#define OMAP_INT_HOST 8
+#define OMAP_INT_ABORT 9
+#define OMAP_INT_BRIDGE_PRIV 13
+#define OMAP_INT_GPIO_BANK1 14
+#define OMAP_INT_UART3 15
+#define OMAP_INT_TIMER3 16
+#define OMAP_INT_DMA_CH0_6 19
+#define OMAP_INT_DMA_CH1_7 20
+#define OMAP_INT_DMA_CH2_8 21
+#define OMAP_INT_DMA_CH3 22
+#define OMAP_INT_DMA_CH4 23
+#define OMAP_INT_DMA_CH5 24
+#define OMAP_INT_DMA_LCD 25
+#define OMAP_INT_TIMER1 26
+#define OMAP_INT_WD_TIMER 27
+#define OMAP_INT_BRIDGE_PUB 28
+#define OMAP_INT_TIMER2 30
+#define OMAP_INT_LCD_CTRL 31
/*
* Common OMAP-15xx IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_15XX_IH2_IRQ 0
-# define OMAP_INT_15XX_LB_MMU 17
-# define OMAP_INT_15XX_LOCAL_BUS 29
+#define OMAP_INT_15XX_IH2_IRQ 0
+#define OMAP_INT_15XX_LB_MMU 17
+#define OMAP_INT_15XX_LOCAL_BUS 29
/*
* OMAP-1510 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_1510_SPI_TX 4
-# define OMAP_INT_1510_SPI_RX 5
-# define OMAP_INT_1510_DSP_MAILBOX1 10
-# define OMAP_INT_1510_DSP_MAILBOX2 11
+#define OMAP_INT_1510_SPI_TX 4
+#define OMAP_INT_1510_SPI_RX 5
+#define OMAP_INT_1510_DSP_MAILBOX1 10
+#define OMAP_INT_1510_DSP_MAILBOX2 11
/*
* OMAP-310 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_310_McBSP2_TX 4
-# define OMAP_INT_310_McBSP2_RX 5
-# define OMAP_INT_310_HSB_MAILBOX1 12
-# define OMAP_INT_310_HSAB_MMU 18
+#define OMAP_INT_310_McBSP2_TX 4
+#define OMAP_INT_310_McBSP2_RX 5
+#define OMAP_INT_310_HSB_MAILBOX1 12
+#define OMAP_INT_310_HSAB_MMU 18
/*
* OMAP-1610 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_1610_IH2_IRQ 0
-# define OMAP_INT_1610_IH2_FIQ 2
-# define OMAP_INT_1610_McBSP2_TX 4
-# define OMAP_INT_1610_McBSP2_RX 5
-# define OMAP_INT_1610_DSP_MAILBOX1 10
-# define OMAP_INT_1610_DSP_MAILBOX2 11
-# define OMAP_INT_1610_LCD_LINE 12
-# define OMAP_INT_1610_GPTIMER1 17
-# define OMAP_INT_1610_GPTIMER2 18
-# define OMAP_INT_1610_SSR_FIFO_0 29
+#define OMAP_INT_1610_IH2_IRQ 0
+#define OMAP_INT_1610_IH2_FIQ 2
+#define OMAP_INT_1610_McBSP2_TX 4
+#define OMAP_INT_1610_McBSP2_RX 5
+#define OMAP_INT_1610_DSP_MAILBOX1 10
+#define OMAP_INT_1610_DSP_MAILBOX2 11
+#define OMAP_INT_1610_LCD_LINE 12
+#define OMAP_INT_1610_GPTIMER1 17
+#define OMAP_INT_1610_GPTIMER2 18
+#define OMAP_INT_1610_SSR_FIFO_0 29
/*
* OMAP-730 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_730_IH2_FIQ 0
-# define OMAP_INT_730_IH2_IRQ 1
-# define OMAP_INT_730_USB_NON_ISO 2
-# define OMAP_INT_730_USB_ISO 3
-# define OMAP_INT_730_ICR 4
-# define OMAP_INT_730_EAC 5
-# define OMAP_INT_730_GPIO_BANK1 6
-# define OMAP_INT_730_GPIO_BANK2 7
-# define OMAP_INT_730_GPIO_BANK3 8
-# define OMAP_INT_730_McBSP2TX 10
-# define OMAP_INT_730_McBSP2RX 11
-# define OMAP_INT_730_McBSP2RX_OVF 12
-# define OMAP_INT_730_LCD_LINE 14
-# define OMAP_INT_730_GSM_PROTECT 15
-# define OMAP_INT_730_TIMER3 16
-# define OMAP_INT_730_GPIO_BANK5 17
-# define OMAP_INT_730_GPIO_BANK6 18
-# define OMAP_INT_730_SPGIO_WR 29
+#define OMAP_INT_730_IH2_FIQ 0
+#define OMAP_INT_730_IH2_IRQ 1
+#define OMAP_INT_730_USB_NON_ISO 2
+#define OMAP_INT_730_USB_ISO 3
+#define OMAP_INT_730_ICR 4
+#define OMAP_INT_730_EAC 5
+#define OMAP_INT_730_GPIO_BANK1 6
+#define OMAP_INT_730_GPIO_BANK2 7
+#define OMAP_INT_730_GPIO_BANK3 8
+#define OMAP_INT_730_McBSP2TX 10
+#define OMAP_INT_730_McBSP2RX 11
+#define OMAP_INT_730_McBSP2RX_OVF 12
+#define OMAP_INT_730_LCD_LINE 14
+#define OMAP_INT_730_GSM_PROTECT 15
+#define OMAP_INT_730_TIMER3 16
+#define OMAP_INT_730_GPIO_BANK5 17
+#define OMAP_INT_730_GPIO_BANK6 18
+#define OMAP_INT_730_SPGIO_WR 29
/*
* Common IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_KEYBOARD 1
-# define OMAP_INT_uWireTX 2
-# define OMAP_INT_uWireRX 3
-# define OMAP_INT_I2C 4
-# define OMAP_INT_MPUIO 5
-# define OMAP_INT_USB_HHC_1 6
-# define OMAP_INT_McBSP3TX 10
-# define OMAP_INT_McBSP3RX 11
-# define OMAP_INT_McBSP1TX 12
-# define OMAP_INT_McBSP1RX 13
-# define OMAP_INT_UART1 14
-# define OMAP_INT_UART2 15
-# define OMAP_INT_USB_W2FC 20
-# define OMAP_INT_1WIRE 21
-# define OMAP_INT_OS_TIMER 22
-# define OMAP_INT_OQN 23
-# define OMAP_INT_GAUGE_32K 24
-# define OMAP_INT_RTC_TIMER 25
-# define OMAP_INT_RTC_ALARM 26
-# define OMAP_INT_DSP_MMU 28
+#define OMAP_INT_KEYBOARD 1
+#define OMAP_INT_uWireTX 2
+#define OMAP_INT_uWireRX 3
+#define OMAP_INT_I2C 4
+#define OMAP_INT_MPUIO 5
+#define OMAP_INT_USB_HHC_1 6
+#define OMAP_INT_McBSP3TX 10
+#define OMAP_INT_McBSP3RX 11
+#define OMAP_INT_McBSP1TX 12
+#define OMAP_INT_McBSP1RX 13
+#define OMAP_INT_UART1 14
+#define OMAP_INT_UART2 15
+#define OMAP_INT_USB_W2FC 20
+#define OMAP_INT_1WIRE 21
+#define OMAP_INT_OS_TIMER 22
+#define OMAP_INT_OQN 23
+#define OMAP_INT_GAUGE_32K 24
+#define OMAP_INT_RTC_TIMER 25
+#define OMAP_INT_RTC_ALARM 26
+#define OMAP_INT_DSP_MMU 28
/*
* OMAP-1510 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_1510_BT_MCSI1TX 16
-# define OMAP_INT_1510_BT_MCSI1RX 17
-# define OMAP_INT_1510_SoSSI_MATCH 19
-# define OMAP_INT_1510_MEM_STICK 27
-# define OMAP_INT_1510_COM_SPI_RO 31
+#define OMAP_INT_1510_BT_MCSI1TX 16
+#define OMAP_INT_1510_BT_MCSI1RX 17
+#define OMAP_INT_1510_SoSSI_MATCH 19
+#define OMAP_INT_1510_MEM_STICK 27
+#define OMAP_INT_1510_COM_SPI_RO 31
/*
* OMAP-310 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_310_FAC 0
-# define OMAP_INT_310_USB_HHC_2 7
-# define OMAP_INT_310_MCSI1_FE 16
-# define OMAP_INT_310_MCSI2_FE 17
-# define OMAP_INT_310_USB_W2FC_ISO 29
-# define OMAP_INT_310_USB_W2FC_NON_ISO 30
-# define OMAP_INT_310_McBSP2RX_OF 31
+#define OMAP_INT_310_FAC 0
+#define OMAP_INT_310_USB_HHC_2 7
+#define OMAP_INT_310_MCSI1_FE 16
+#define OMAP_INT_310_MCSI2_FE 17
+#define OMAP_INT_310_USB_W2FC_ISO 29
+#define OMAP_INT_310_USB_W2FC_NON_ISO 30
+#define OMAP_INT_310_McBSP2RX_OF 31
/*
* OMAP-1610 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_1610_FAC 0
-# define OMAP_INT_1610_USB_HHC_2 7
-# define OMAP_INT_1610_USB_OTG 8
-# define OMAP_INT_1610_SoSSI 9
-# define OMAP_INT_1610_BT_MCSI1TX 16
-# define OMAP_INT_1610_BT_MCSI1RX 17
-# define OMAP_INT_1610_SoSSI_MATCH 19
-# define OMAP_INT_1610_MEM_STICK 27
-# define OMAP_INT_1610_McBSP2RX_OF 31
-# define OMAP_INT_1610_STI 32
-# define OMAP_INT_1610_STI_WAKEUP 33
-# define OMAP_INT_1610_GPTIMER3 34
-# define OMAP_INT_1610_GPTIMER4 35
-# define OMAP_INT_1610_GPTIMER5 36
-# define OMAP_INT_1610_GPTIMER6 37
-# define OMAP_INT_1610_GPTIMER7 38
-# define OMAP_INT_1610_GPTIMER8 39
-# define OMAP_INT_1610_GPIO_BANK2 40
-# define OMAP_INT_1610_GPIO_BANK3 41
-# define OMAP_INT_1610_MMC2 42
-# define OMAP_INT_1610_CF 43
-# define OMAP_INT_1610_WAKE_UP_REQ 46
-# define OMAP_INT_1610_GPIO_BANK4 48
-# define OMAP_INT_1610_SPI 49
-# define OMAP_INT_1610_DMA_CH6 53
-# define OMAP_INT_1610_DMA_CH7 54
-# define OMAP_INT_1610_DMA_CH8 55
-# define OMAP_INT_1610_DMA_CH9 56
-# define OMAP_INT_1610_DMA_CH10 57
-# define OMAP_INT_1610_DMA_CH11 58
-# define OMAP_INT_1610_DMA_CH12 59
-# define OMAP_INT_1610_DMA_CH13 60
-# define OMAP_INT_1610_DMA_CH14 61
-# define OMAP_INT_1610_DMA_CH15 62
-# define OMAP_INT_1610_NAND 63
+#define OMAP_INT_1610_FAC 0
+#define OMAP_INT_1610_USB_HHC_2 7
+#define OMAP_INT_1610_USB_OTG 8
+#define OMAP_INT_1610_SoSSI 9
+#define OMAP_INT_1610_BT_MCSI1TX 16
+#define OMAP_INT_1610_BT_MCSI1RX 17
+#define OMAP_INT_1610_SoSSI_MATCH 19
+#define OMAP_INT_1610_MEM_STICK 27
+#define OMAP_INT_1610_McBSP2RX_OF 31
+#define OMAP_INT_1610_STI 32
+#define OMAP_INT_1610_STI_WAKEUP 33
+#define OMAP_INT_1610_GPTIMER3 34
+#define OMAP_INT_1610_GPTIMER4 35
+#define OMAP_INT_1610_GPTIMER5 36
+#define OMAP_INT_1610_GPTIMER6 37
+#define OMAP_INT_1610_GPTIMER7 38
+#define OMAP_INT_1610_GPTIMER8 39
+#define OMAP_INT_1610_GPIO_BANK2 40
+#define OMAP_INT_1610_GPIO_BANK3 41
+#define OMAP_INT_1610_MMC2 42
+#define OMAP_INT_1610_CF 43
+#define OMAP_INT_1610_WAKE_UP_REQ 46
+#define OMAP_INT_1610_GPIO_BANK4 48
+#define OMAP_INT_1610_SPI 49
+#define OMAP_INT_1610_DMA_CH6 53
+#define OMAP_INT_1610_DMA_CH7 54
+#define OMAP_INT_1610_DMA_CH8 55
+#define OMAP_INT_1610_DMA_CH9 56
+#define OMAP_INT_1610_DMA_CH10 57
+#define OMAP_INT_1610_DMA_CH11 58
+#define OMAP_INT_1610_DMA_CH12 59
+#define OMAP_INT_1610_DMA_CH13 60
+#define OMAP_INT_1610_DMA_CH14 61
+#define OMAP_INT_1610_DMA_CH15 62
+#define OMAP_INT_1610_NAND 63
/*
* OMAP-730 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_730_HW_ERRORS 0
-# define OMAP_INT_730_NFIQ_PWR_FAIL 1
-# define OMAP_INT_730_CFCD 2
-# define OMAP_INT_730_CFIREQ 3
-# define OMAP_INT_730_I2C 4
-# define OMAP_INT_730_PCC 5
-# define OMAP_INT_730_MPU_EXT_NIRQ 6
-# define OMAP_INT_730_SPI_100K_1 7
-# define OMAP_INT_730_SYREN_SPI 8
-# define OMAP_INT_730_VLYNQ 9
-# define OMAP_INT_730_GPIO_BANK4 10
-# define OMAP_INT_730_McBSP1TX 11
-# define OMAP_INT_730_McBSP1RX 12
-# define OMAP_INT_730_McBSP1RX_OF 13
-# define OMAP_INT_730_UART_MODEM_IRDA_2 14
-# define OMAP_INT_730_UART_MODEM_1 15
-# define OMAP_INT_730_MCSI 16
-# define OMAP_INT_730_uWireTX 17
-# define OMAP_INT_730_uWireRX 18
-# define OMAP_INT_730_SMC_CD 19
-# define OMAP_INT_730_SMC_IREQ 20
-# define OMAP_INT_730_HDQ_1WIRE 21
-# define OMAP_INT_730_TIMER32K 22
-# define OMAP_INT_730_MMC_SDIO 23
-# define OMAP_INT_730_UPLD 24
-# define OMAP_INT_730_USB_HHC_1 27
-# define OMAP_INT_730_USB_HHC_2 28
-# define OMAP_INT_730_USB_GENI 29
-# define OMAP_INT_730_USB_OTG 30
-# define OMAP_INT_730_CAMERA_IF 31
-# define OMAP_INT_730_RNG 32
-# define OMAP_INT_730_DUAL_MODE_TIMER 33
-# define OMAP_INT_730_DBB_RF_EN 34
-# define OMAP_INT_730_MPUIO_KEYPAD 35
-# define OMAP_INT_730_SHA1_MD5 36
-# define OMAP_INT_730_SPI_100K_2 37
-# define OMAP_INT_730_RNG_IDLE 38
-# define OMAP_INT_730_MPUIO 39
-# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
-# define OMAP_INT_730_LLPC_OE_FALLING 41
-# define OMAP_INT_730_LLPC_OE_RISING 42
-# define OMAP_INT_730_LLPC_VSYNC 43
-# define OMAP_INT_730_WAKE_UP_REQ 46
-# define OMAP_INT_730_DMA_CH6 53
-# define OMAP_INT_730_DMA_CH7 54
-# define OMAP_INT_730_DMA_CH8 55
-# define OMAP_INT_730_DMA_CH9 56
-# define OMAP_INT_730_DMA_CH10 57
-# define OMAP_INT_730_DMA_CH11 58
-# define OMAP_INT_730_DMA_CH12 59
-# define OMAP_INT_730_DMA_CH13 60
-# define OMAP_INT_730_DMA_CH14 61
-# define OMAP_INT_730_DMA_CH15 62
-# define OMAP_INT_730_NAND 63
+#define OMAP_INT_730_HW_ERRORS 0
+#define OMAP_INT_730_NFIQ_PWR_FAIL 1
+#define OMAP_INT_730_CFCD 2
+#define OMAP_INT_730_CFIREQ 3
+#define OMAP_INT_730_I2C 4
+#define OMAP_INT_730_PCC 5
+#define OMAP_INT_730_MPU_EXT_NIRQ 6
+#define OMAP_INT_730_SPI_100K_1 7
+#define OMAP_INT_730_SYREN_SPI 8
+#define OMAP_INT_730_VLYNQ 9
+#define OMAP_INT_730_GPIO_BANK4 10
+#define OMAP_INT_730_McBSP1TX 11
+#define OMAP_INT_730_McBSP1RX 12
+#define OMAP_INT_730_McBSP1RX_OF 13
+#define OMAP_INT_730_UART_MODEM_IRDA_2 14
+#define OMAP_INT_730_UART_MODEM_1 15
+#define OMAP_INT_730_MCSI 16
+#define OMAP_INT_730_uWireTX 17
+#define OMAP_INT_730_uWireRX 18
+#define OMAP_INT_730_SMC_CD 19
+#define OMAP_INT_730_SMC_IREQ 20
+#define OMAP_INT_730_HDQ_1WIRE 21
+#define OMAP_INT_730_TIMER32K 22
+#define OMAP_INT_730_MMC_SDIO 23
+#define OMAP_INT_730_UPLD 24
+#define OMAP_INT_730_USB_HHC_1 27
+#define OMAP_INT_730_USB_HHC_2 28
+#define OMAP_INT_730_USB_GENI 29
+#define OMAP_INT_730_USB_OTG 30
+#define OMAP_INT_730_CAMERA_IF 31
+#define OMAP_INT_730_RNG 32
+#define OMAP_INT_730_DUAL_MODE_TIMER 33
+#define OMAP_INT_730_DBB_RF_EN 34
+#define OMAP_INT_730_MPUIO_KEYPAD 35
+#define OMAP_INT_730_SHA1_MD5 36
+#define OMAP_INT_730_SPI_100K_2 37
+#define OMAP_INT_730_RNG_IDLE 38
+#define OMAP_INT_730_MPUIO 39
+#define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
+#define OMAP_INT_730_LLPC_OE_FALLING 41
+#define OMAP_INT_730_LLPC_OE_RISING 42
+#define OMAP_INT_730_LLPC_VSYNC 43
+#define OMAP_INT_730_WAKE_UP_REQ 46
+#define OMAP_INT_730_DMA_CH6 53
+#define OMAP_INT_730_DMA_CH7 54
+#define OMAP_INT_730_DMA_CH8 55
+#define OMAP_INT_730_DMA_CH9 56
+#define OMAP_INT_730_DMA_CH10 57
+#define OMAP_INT_730_DMA_CH11 58
+#define OMAP_INT_730_DMA_CH12 59
+#define OMAP_INT_730_DMA_CH13 60
+#define OMAP_INT_730_DMA_CH14 61
+#define OMAP_INT_730_DMA_CH15 62
+#define OMAP_INT_730_NAND 63
/* omap_dma.c */
enum omap_dma_model {
@@ -353,9 +353,9 @@ struct dma_irq_map {
enum omap_dma_port {
emiff = 0,
emifs,
- imif, /* omap16xx: ocp_t1 */
+ imif, /* omap16xx: ocp_t1 */
tipb,
- local, /* omap16xx: ocp_t2 */
+ local, /* omap16xx: ocp_t2 */
tipb_mpui,
__omap_dma_port_last,
};
@@ -418,65 +418,65 @@ struct omap_dma_lcd_channel_s {
* DMA request numbers for OMAP1
* See /usr/include/asm-arm/arch-omap/dma.h in Linux.
*/
-# define OMAP_DMA_NO_DEVICE 0
-# define OMAP_DMA_MCSI1_TX 1
-# define OMAP_DMA_MCSI1_RX 2
-# define OMAP_DMA_I2C_RX 3
-# define OMAP_DMA_I2C_TX 4
-# define OMAP_DMA_EXT_NDMA_REQ0 5
-# define OMAP_DMA_EXT_NDMA_REQ1 6
-# define OMAP_DMA_UWIRE_TX 7
-# define OMAP_DMA_MCBSP1_TX 8
-# define OMAP_DMA_MCBSP1_RX 9
-# define OMAP_DMA_MCBSP3_TX 10
-# define OMAP_DMA_MCBSP3_RX 11
-# define OMAP_DMA_UART1_TX 12
-# define OMAP_DMA_UART1_RX 13
-# define OMAP_DMA_UART2_TX 14
-# define OMAP_DMA_UART2_RX 15
-# define OMAP_DMA_MCBSP2_TX 16
-# define OMAP_DMA_MCBSP2_RX 17
-# define OMAP_DMA_UART3_TX 18
-# define OMAP_DMA_UART3_RX 19
-# define OMAP_DMA_CAMERA_IF_RX 20
-# define OMAP_DMA_MMC_TX 21
-# define OMAP_DMA_MMC_RX 22
-# define OMAP_DMA_NAND 23 /* Not in OMAP310 */
-# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
-# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
-# define OMAP_DMA_USB_W2FC_RX0 26
-# define OMAP_DMA_USB_W2FC_RX1 27
-# define OMAP_DMA_USB_W2FC_RX2 28
-# define OMAP_DMA_USB_W2FC_TX0 29
-# define OMAP_DMA_USB_W2FC_TX1 30
-# define OMAP_DMA_USB_W2FC_TX2 31
+#define OMAP_DMA_NO_DEVICE 0
+#define OMAP_DMA_MCSI1_TX 1
+#define OMAP_DMA_MCSI1_RX 2
+#define OMAP_DMA_I2C_RX 3
+#define OMAP_DMA_I2C_TX 4
+#define OMAP_DMA_EXT_NDMA_REQ0 5
+#define OMAP_DMA_EXT_NDMA_REQ1 6
+#define OMAP_DMA_UWIRE_TX 7
+#define OMAP_DMA_MCBSP1_TX 8
+#define OMAP_DMA_MCBSP1_RX 9
+#define OMAP_DMA_MCBSP3_TX 10
+#define OMAP_DMA_MCBSP3_RX 11
+#define OMAP_DMA_UART1_TX 12
+#define OMAP_DMA_UART1_RX 13
+#define OMAP_DMA_UART2_TX 14
+#define OMAP_DMA_UART2_RX 15
+#define OMAP_DMA_MCBSP2_TX 16
+#define OMAP_DMA_MCBSP2_RX 17
+#define OMAP_DMA_UART3_TX 18
+#define OMAP_DMA_UART3_RX 19
+#define OMAP_DMA_CAMERA_IF_RX 20
+#define OMAP_DMA_MMC_TX 21
+#define OMAP_DMA_MMC_RX 22
+#define OMAP_DMA_NAND 23 /* Not in OMAP310 */
+#define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
+#define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
+#define OMAP_DMA_USB_W2FC_RX0 26
+#define OMAP_DMA_USB_W2FC_RX1 27
+#define OMAP_DMA_USB_W2FC_RX2 28
+#define OMAP_DMA_USB_W2FC_TX0 29
+#define OMAP_DMA_USB_W2FC_TX1 30
+#define OMAP_DMA_USB_W2FC_TX2 31
/* These are only for 1610 */
-# define OMAP_DMA_CRYPTO_DES_IN 32
-# define OMAP_DMA_SPI_TX 33
-# define OMAP_DMA_SPI_RX 34
-# define OMAP_DMA_CRYPTO_HASH 35
-# define OMAP_DMA_CCP_ATTN 36
-# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
-# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
-# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
-# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
-# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
-# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
-# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
-# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
-# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
-# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
-# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
-# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
-# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
-# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
-# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
-# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
-# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
-# define OMAP_DMA_MMC2_TX 54
-# define OMAP_DMA_MMC2_RX 55
-# define OMAP_DMA_CRYPTO_DES_OUT 56
+#define OMAP_DMA_CRYPTO_DES_IN 32
+#define OMAP_DMA_SPI_TX 33
+#define OMAP_DMA_SPI_RX 34
+#define OMAP_DMA_CRYPTO_HASH 35
+#define OMAP_DMA_CCP_ATTN 36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
+#define OMAP_DMA_MMC2_TX 54
+#define OMAP_DMA_MMC2_RX 55
+#define OMAP_DMA_CRYPTO_DES_OUT 56
struct omap_uart_s;
struct omap_uart_s *omap_uart_init(hwaddr base,
@@ -542,14 +542,14 @@ void omap_mmc_set_clk(DeviceState *dev, omap_clk clk);
/* omap_i2c.c */
I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
-# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
-# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
-# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
-# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
+#define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
+#define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
+#define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
+#define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
-# define cpu_is_omap15xx(cpu) \
+#define cpu_is_omap15xx(cpu) \
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
-# define cpu_is_omap16xx(cpu) \
+#define cpu_is_omap16xx(cpu) \
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
struct omap_mpu_state_s {
@@ -685,14 +685,14 @@ void omap_badwidth_write32(void *opaque, hwaddr addr,
void omap_mpu_wakeup(void *opaque, int irq, int req);
-# define OMAP_BAD_REG(paddr) \
+#define OMAP_BAD_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
__func__, paddr)
-# define OMAP_RO_REG(paddr) \
+#define OMAP_RO_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
HWADDR_PRIx "\n", \
__func__, paddr)
-# define OMAP_MPUI_REG_MASK 0x000007ff
+#define OMAP_MPUI_REG_MASK 0x000007ff
#endif
diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
deleted file mode 100644
index e986b28..0000000
--- a/include/hw/arm/sharpsl.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Common declarations for the Zaurii.
- *
- * This file is licensed under the GNU GPL.
- */
-
-#ifndef QEMU_SHARPSL_H
-#define QEMU_SHARPSL_H
-
-#include "exec/hwaddr.h"
-
-/* zaurus.c */
-
-#define SL_PXA_PARAM_BASE 0xa0000a00
-void sl_bootparam_write(hwaddr ptr);
-
-#endif
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index e5e2d09..80d0fec 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -161,6 +161,7 @@ struct SMMUState {
QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
uint8_t bus_num;
PCIBus *primary_bus;
+ bool smmu_per_bus; /* SMMU is specific to the primary_bus */
};
struct SMMUBaseClass {
diff --git a/include/hw/arm/soc_dma.h b/include/hw/arm/soc_dma.h
index e93a749..bcdb914 100644
--- a/include/hw/arm/soc_dma.h
+++ b/include/hw/arm/soc_dma.h
@@ -54,7 +54,7 @@ struct soc_dma_ch_s {
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
- hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
+ hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -70,7 +70,7 @@ struct soc_dma_ch_s {
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
- uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
+ uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 4f4c8bb..46eda34 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -59,7 +59,7 @@ struct STM32F205State {
STM32F2XXADCState adc[STM_NUM_ADCS];
STM32F2XXSPIState spi[STM_NUM_SPIS];
- OrIRQState *adc_irqs;
+ OrIRQState adc_irqs;
MemoryRegion sram;
MemoryRegion flash;
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index c243fb0..c2fae6e 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -24,7 +24,7 @@
#ifndef HW_ARM_STM32L4x5_SOC_H
#define HW_ARM_STM32L4x5_SOC_H
-#include "exec/memory.h"
+#include "system/memory.h"
#include "hw/arm/armv7m.h"
#include "hw/or-irq.h"
#include "hw/misc/stm32l4x5_syscfg.h"
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index c8e94e6..04a09af 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -33,9 +33,11 @@
#include "exec/hwaddr.h"
#include "qemu/notify.h"
#include "hw/boards.h"
+#include "hw/acpi/ghes.h"
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
#include "hw/block/flash.h"
+#include "hw/cxl/cxl.h"
#include "system/kvm.h"
#include "hw/intc/arm_gicv3_common.h"
#include "qom/object.h"
@@ -79,12 +81,14 @@ enum {
VIRT_ACPI_GED,
VIRT_NVDIMM_ACPI,
VIRT_PVTIME,
+ VIRT_ACPI_PCIHP,
VIRT_LOWMEMMAP_LAST,
};
/* indices of IO regions located after the RAM */
enum {
VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
+ VIRT_CXL_HOST,
VIRT_HIGH_PCIE_ECAM,
VIRT_HIGH_PCIE_MMIO,
};
@@ -117,14 +121,8 @@ typedef enum VirtGICType {
struct VirtMachineClass {
MachineClass parent;
- bool disallow_affinity_adjustment;
- bool no_its;
bool no_tcg_its;
- bool no_pmu;
- bool claim_edge_triggered_timers;
- bool smbios_old_sys_ver;
bool no_highmem_compact;
- bool no_highmem_ecam;
bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
bool kvm_no_adjvtime;
bool no_kvm_steal_time;
@@ -146,6 +144,7 @@ struct VirtMachineState {
bool secure;
bool highmem;
bool highmem_compact;
+ bool highmem_cxl;
bool highmem_ecam;
bool highmem_mmio;
bool highmem_redists;
@@ -176,10 +175,13 @@ struct VirtMachineState {
DeviceState *gic;
DeviceState *acpi_dev;
Notifier powerdown_notifier;
+ Notifier generic_error_notifier;
PCIBus *bus;
char *oem_id;
char *oem_table_id;
bool ns_el2_virt_timer_irq;
+ CXLState cxl_devices_state;
+ bool legacy_smmuv3_present;
};
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
diff --git a/include/hw/arm/xen_arch_hvm.h b/include/hw/arm/xen_arch_hvm.h
deleted file mode 100644
index 8fd645e..0000000
--- a/include/hw/arm/xen_arch_hvm.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef HW_XEN_ARCH_ARM_HVM_H
-#define HW_XEN_ARCH_ARM_HVM_H
-
-#include <xen/hvm/ioreq.h>
-void arch_handle_ioreq(XenIOState *state, ioreq_t *req);
-void arch_xen_set_memory(XenIOState *state,
- MemoryRegionSection *section,
- bool add);
-#endif
diff --git a/include/hw/arm/xlnx-versal-version.h b/include/hw/arm/xlnx-versal-version.h
new file mode 100644
index 0000000..5b6b6e5
--- /dev/null
+++ b/include/hw/arm/xlnx-versal-version.h
@@ -0,0 +1,16 @@
+/*
+ * AMD Versal versions
+ *
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_ARM_XLNX_VERSAL_VERSION_H
+#define HW_ARM_XLNX_VERSAL_VERSION_H
+
+typedef enum VersalVersion {
+ VERSAL_VER_VERSAL,
+ VERSAL_VER_VERSAL2,
+} VersalVersion;
+
+#endif
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 05ed641..e1fb1f4 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -1,7 +1,8 @@
/*
- * Model of the Xilinx Versal
+ * AMD/Xilinx Versal family SoC model.
*
* Copyright (c) 2018 Xilinx Inc.
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
* Written by Edgar E. Iglesias
*
* This program is free software; you can redistribute it and/or modify
@@ -13,326 +14,77 @@
#define XLNX_VERSAL_H
#include "hw/sysbus.h"
-#include "hw/cpu/cluster.h"
-#include "hw/or-irq.h"
-#include "hw/sd/sdhci.h"
-#include "hw/intc/arm_gicv3.h"
-#include "hw/char/pl011.h"
-#include "hw/dma/xlnx-zdma.h"
-#include "hw/net/cadence_gem.h"
-#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
-#include "hw/usb/xlnx-usb-subsystem.h"
-#include "hw/misc/xlnx-versal-xramc.h"
-#include "hw/nvram/xlnx-bbram.h"
-#include "hw/nvram/xlnx-versal-efuse.h"
-#include "hw/ssi/xlnx-versal-ospi.h"
-#include "hw/dma/xlnx_csu_dma.h"
-#include "hw/misc/xlnx-versal-crl.h"
-#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
-#include "hw/misc/xlnx-versal-trng.h"
-#include "hw/net/xlnx-versal-canfd.h"
-#include "hw/misc/xlnx-versal-cfu.h"
-#include "hw/misc/xlnx-versal-cframe-reg.h"
-#include "target/arm/cpu.h"
+#include "net/can_emu.h"
+#include "hw/arm/xlnx-versal-version.h"
-#define TYPE_XLNX_VERSAL "xlnx-versal"
-OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
+#define TYPE_XLNX_VERSAL_BASE "xlnx-versal-base"
+OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BASE)
-#define XLNX_VERSAL_NR_ACPUS 2
-#define XLNX_VERSAL_NR_RCPUS 2
-#define XLNX_VERSAL_NR_UARTS 2
-#define XLNX_VERSAL_NR_GEMS 2
-#define XLNX_VERSAL_NR_ADMAS 8
-#define XLNX_VERSAL_NR_SDS 2
-#define XLNX_VERSAL_NR_XRAM 4
-#define XLNX_VERSAL_NR_IRQS 192
-#define XLNX_VERSAL_NR_CANFD 2
-#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
-#define XLNX_VERSAL_NR_CFRAME 15
+#define TYPE_XLNX_VERSAL "xlnx-versal"
+#define TYPE_XLNX_VERSAL2 "xlnx-versal2"
struct Versal {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
- struct {
- struct {
- MemoryRegion mr;
- CPUClusterState cluster;
- ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
- GICv3State gic;
- } apu;
- } fpd;
-
+ GArray *intc;
MemoryRegion mr_ps;
struct {
- /* 4 ranges to access DDR. */
- MemoryRegion mr_ddr_ranges[4];
- } noc;
-
- struct {
- MemoryRegion mr_ocm;
-
- struct {
- PL011State uart[XLNX_VERSAL_NR_UARTS];
- CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
- OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS];
- XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
- VersalUsb2 usb;
- CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
- XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD];
- } iou;
-
- /* Real-time Processing Unit. */
- struct {
- MemoryRegion mr;
- MemoryRegion mr_ps_alias;
-
- CPUClusterState cluster;
- ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
- } rpu;
-
- struct {
- OrIRQState irq_orgate;
- XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
- } xram;
-
- XlnxVersalCRL crl;
- } lpd;
-
- /* The Platform Management Controller subsystem. */
- struct {
- struct {
- SDHCIState sd[XLNX_VERSAL_NR_SDS];
- XlnxVersalPmcIouSlcr slcr;
-
- struct {
- XlnxVersalOspi ospi;
- XlnxCSUDMA dma_src;
- XlnxCSUDMA dma_dst;
- MemoryRegion linear_mr;
- OrIRQState irq_orgate;
- } ospi;
- } iou;
-
- XlnxZynqMPRTC rtc;
- XlnxVersalTRng trng;
- XlnxBBRam bbram;
- XlnxEFuse efuse;
- XlnxVersalEFuseCtrl efuse_ctrl;
- XlnxVersalEFuseCache efuse_cache;
- XlnxVersalCFUAPB cfu_apb;
- XlnxVersalCFUFDRO cfu_fdro;
- XlnxVersalCFUSFR cfu_sfr;
- XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
- XlnxVersalCFrameBcastReg cframe_bcast;
-
- OrIRQState apb_irq_orgate;
- } pmc;
+ uint32_t clk_25mhz;
+ uint32_t clk_125mhz;
+ uint32_t gic;
+ } phandle;
struct {
MemoryRegion *mr_ddr;
+ CanBusState **canbus;
+ void *fdt;
} cfg;
};
-/* Memory-map and IRQ definitions. Copied a subset from
- * auto-generated files. */
-
-#define VERSAL_GIC_MAINT_IRQ 9
-#define VERSAL_TIMER_VIRT_IRQ 11
-#define VERSAL_TIMER_S_EL1_IRQ 13
-#define VERSAL_TIMER_NS_EL1_IRQ 14
-#define VERSAL_TIMER_NS_EL2_IRQ 10
-
-#define VERSAL_CRL_IRQ 10
-#define VERSAL_UART0_IRQ_0 18
-#define VERSAL_UART1_IRQ_0 19
-#define VERSAL_CANFD0_IRQ_0 20
-#define VERSAL_CANFD1_IRQ_0 21
-#define VERSAL_USB0_IRQ_0 22
-#define VERSAL_GEM0_IRQ_0 56
-#define VERSAL_GEM0_WAKE_IRQ_0 57
-#define VERSAL_GEM1_IRQ_0 58
-#define VERSAL_GEM1_WAKE_IRQ_0 59
-#define VERSAL_ADMA_IRQ_0 60
-#define VERSAL_XRAM_IRQ_0 79
-#define VERSAL_CFU_IRQ_0 120
-#define VERSAL_PMC_APB_IRQ 121
-#define VERSAL_OSPI_IRQ 124
-#define VERSAL_SD0_IRQ_0 126
-#define VERSAL_EFUSE_IRQ 139
-#define VERSAL_TRNG_IRQ 141
-#define VERSAL_RTC_ALARM_IRQ 142
-#define VERSAL_RTC_SECONDS_IRQ 143
-
-/* Architecturally reserved IRQs suitable for virtualization. */
-#define VERSAL_RSVD_IRQ_FIRST 111
-#define VERSAL_RSVD_IRQ_LAST 118
-
-#define MM_TOP_RSVD 0xa0000000U
-#define MM_TOP_RSVD_SIZE 0x4000000
-#define MM_GIC_APU_DIST_MAIN 0xf9000000U
-#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
-#define MM_GIC_APU_REDIST_0 0xf9080000U
-#define MM_GIC_APU_REDIST_0_SIZE 0x80000
-
-#define MM_UART0 0xff000000U
-#define MM_UART0_SIZE 0x10000
-#define MM_UART1 0xff010000U
-#define MM_UART1_SIZE 0x10000
-
-#define MM_CANFD0 0xff060000U
-#define MM_CANFD0_SIZE 0x10000
-#define MM_CANFD1 0xff070000U
-#define MM_CANFD1_SIZE 0x10000
-
-#define MM_GEM0 0xff0c0000U
-#define MM_GEM0_SIZE 0x10000
-#define MM_GEM1 0xff0d0000U
-#define MM_GEM1_SIZE 0x10000
+struct VersalClass {
+ SysBusDeviceClass parent;
-#define MM_ADMA_CH0 0xffa80000U
-#define MM_ADMA_CH0_SIZE 0x10000
-
-#define MM_OCM 0xfffc0000U
-#define MM_OCM_SIZE 0x40000
-
-#define MM_XRAM 0xfe800000
-#define MM_XRAMC 0xff8e0000
-#define MM_XRAMC_SIZE 0x10000
-
-#define MM_USB2_CTRL_REGS 0xFF9D0000
-#define MM_USB2_CTRL_REGS_SIZE 0x10000
-
-#define MM_USB_0 0xFE200000
-#define MM_USB_0_SIZE 0x10000
-
-#define MM_TOP_DDR 0x0
-#define MM_TOP_DDR_SIZE 0x80000000U
-#define MM_TOP_DDR_2 0x800000000ULL
-#define MM_TOP_DDR_2_SIZE 0x800000000ULL
-#define MM_TOP_DDR_3 0xc000000000ULL
-#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
-#define MM_TOP_DDR_4 0x10000000000ULL
-#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
-
-#define MM_PSM_START 0xffc80000U
-#define MM_PSM_END 0xffcf0000U
+ VersalVersion version;
+};
-#define MM_CRL 0xff5e0000U
-#define MM_CRL_SIZE 0x300000
-#define MM_IOU_SCNTR 0xff130000U
-#define MM_IOU_SCNTR_SIZE 0x10000
-#define MM_IOU_SCNTRS 0xff140000U
-#define MM_IOU_SCNTRS_SIZE 0x10000
-#define MM_FPD_CRF 0xfd1a0000U
-#define MM_FPD_CRF_SIZE 0x140000
-#define MM_FPD_FPD_APU 0xfd5c0000
-#define MM_FPD_FPD_APU_SIZE 0x100
+static inline void versal_set_fdt(Versal *s, void *fdt)
+{
+ g_assert(!qdev_is_realized(DEVICE(s)));
+ s->cfg.fdt = fdt;
+}
-#define MM_PMC_PMC_IOU_SLCR 0xf1060000
-#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
+void versal_fdt_add_memory_nodes(Versal *s, uint64_t ram_size);
-#define MM_PMC_OSPI 0xf1010000
-#define MM_PMC_OSPI_SIZE 0x10000
+DeviceState *versal_get_boot_cpu(Versal *s);
+void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk);
+void versal_efuse_attach_drive(Versal *s, BlockBackend *blk);
+void versal_bbram_attach_drive(Versal *s, BlockBackend *blk);
+void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
+ BlockBackend *blk);
-#define MM_PMC_OSPI_DAC 0xc0000000
-#define MM_PMC_OSPI_DAC_SIZE 0x20000000
+qemu_irq versal_get_reserved_irq(Versal *s, int idx, int *dtb_idx);
+hwaddr versal_get_reserved_mmio_addr(Versal *s);
-#define MM_PMC_OSPI_DMA_DST 0xf1011800
-#define MM_PMC_OSPI_DMA_SRC 0xf1011000
+int versal_get_num_cpu(VersalVersion version);
+int versal_get_num_can(VersalVersion version);
+int versal_get_num_sdhci(VersalVersion version);
-#define MM_PMC_SD0 0xf1040000U
-#define MM_PMC_SD0_SIZE 0x10000
-#define MM_PMC_BBRAM_CTRL 0xf11f0000
-#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
-#define MM_PMC_EFUSE_CTRL 0xf1240000
-#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
-#define MM_PMC_EFUSE_CACHE 0xf1250000
-#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
+static inline const char *versal_get_class(VersalVersion version)
+{
+ switch (version) {
+ case VERSAL_VER_VERSAL:
+ return TYPE_XLNX_VERSAL;
-#define MM_PMC_CFU_APB 0xf12b0000
-#define MM_PMC_CFU_APB_SIZE 0x10000
-#define MM_PMC_CFU_STREAM 0xf12c0000
-#define MM_PMC_CFU_STREAM_SIZE 0x1000
-#define MM_PMC_CFU_SFR 0xf12c1000
-#define MM_PMC_CFU_SFR_SIZE 0x1000
-#define MM_PMC_CFU_FDRO 0xf12c2000
-#define MM_PMC_CFU_FDRO_SIZE 0x1000
-#define MM_PMC_CFU_STREAM_2 0xf1f80000
-#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
+ case VERSAL_VER_VERSAL2:
+ return TYPE_XLNX_VERSAL2;
-#define MM_PMC_CFRAME0_REG 0xf12d0000
-#define MM_PMC_CFRAME0_REG_SIZE 0x1000
-#define MM_PMC_CFRAME0_FDRI 0xf12d1000
-#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME1_REG 0xf12d2000
-#define MM_PMC_CFRAME1_REG_SIZE 0x1000
-#define MM_PMC_CFRAME1_FDRI 0xf12d3000
-#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME2_REG 0xf12d4000
-#define MM_PMC_CFRAME2_REG_SIZE 0x1000
-#define MM_PMC_CFRAME2_FDRI 0xf12d5000
-#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME3_REG 0xf12d6000
-#define MM_PMC_CFRAME3_REG_SIZE 0x1000
-#define MM_PMC_CFRAME3_FDRI 0xf12d7000
-#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME4_REG 0xf12d8000
-#define MM_PMC_CFRAME4_REG_SIZE 0x1000
-#define MM_PMC_CFRAME4_FDRI 0xf12d9000
-#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME5_REG 0xf12da000
-#define MM_PMC_CFRAME5_REG_SIZE 0x1000
-#define MM_PMC_CFRAME5_FDRI 0xf12db000
-#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME6_REG 0xf12dc000
-#define MM_PMC_CFRAME6_REG_SIZE 0x1000
-#define MM_PMC_CFRAME6_FDRI 0xf12dd000
-#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME7_REG 0xf12de000
-#define MM_PMC_CFRAME7_REG_SIZE 0x1000
-#define MM_PMC_CFRAME7_FDRI 0xf12df000
-#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME8_REG 0xf12e0000
-#define MM_PMC_CFRAME8_REG_SIZE 0x1000
-#define MM_PMC_CFRAME8_FDRI 0xf12e1000
-#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME9_REG 0xf12e2000
-#define MM_PMC_CFRAME9_REG_SIZE 0x1000
-#define MM_PMC_CFRAME9_FDRI 0xf12e3000
-#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME10_REG 0xf12e4000
-#define MM_PMC_CFRAME10_REG_SIZE 0x1000
-#define MM_PMC_CFRAME10_FDRI 0xf12e5000
-#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME11_REG 0xf12e6000
-#define MM_PMC_CFRAME11_REG_SIZE 0x1000
-#define MM_PMC_CFRAME11_FDRI 0xf12e7000
-#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME12_REG 0xf12e8000
-#define MM_PMC_CFRAME12_REG_SIZE 0x1000
-#define MM_PMC_CFRAME12_FDRI 0xf12e9000
-#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME13_REG 0xf12ea000
-#define MM_PMC_CFRAME13_REG_SIZE 0x1000
-#define MM_PMC_CFRAME13_FDRI 0xf12eb000
-#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME14_REG 0xf12ec000
-#define MM_PMC_CFRAME14_REG_SIZE 0x1000
-#define MM_PMC_CFRAME14_FDRI 0xf12ed000
-#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
-#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
-#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
-#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
-#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
+ default:
+ g_assert_not_reached();
+ }
+}
-#define MM_PMC_CRP 0xf1260000U
-#define MM_PMC_CRP_SIZE 0x10000
-#define MM_PMC_RTC 0xf12a0000
-#define MM_PMC_RTC_SIZE 0x10000
-#define MM_PMC_TRNG 0xf1230000
-#define MM_PMC_TRNG_SIZE 0x10000
#endif
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c137ac5..a3117bd 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -42,6 +42,7 @@
#include "hw/misc/xlnx-zynqmp-crf.h"
#include "hw/timer/cadence_ttc.h"
#include "hw/usb/hcd-dwc3.h"
+#include "hw/core/split-irq.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -67,6 +68,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
#define XLNX_ZYNQMP_GIC_REGIONS 6
+#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160
/*
* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
@@ -105,6 +107,9 @@ struct XlnxZynqMPState {
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
+ GICState rpu_gic;
+ SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
+
MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
MemoryRegion *ddr_ram;
generated by cgit v1.1 at 2025-10-17 13:20:10 +0000