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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-09 09:08:56 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:56 +0100 |
| commit | c50eaed135216597cd75f71cec79ae28a7996c06 (patch) | |
| tree | a4d1adf0afceff902efa362d20f0e3f37b8a9097 /ui | |
| parent | 8f8c7932d4be3fe4dc0fb9540c48132de7382cab (diff) | |
| download | qemu-c50eaed135216597cd75f71cec79ae28a7996c06.zip qemu-c50eaed135216597cd75f71cec79ae28a7996c06.tar.gz qemu-c50eaed135216597cd75f71cec79ae28a7996c06.tar.bz2 | |
target/ppc: 6xx: Set SRRs directly in exception code
The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'ui')
0 files changed, 0 insertions, 0 deletions