Supply missing header guards

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190604181618.19980-5-armbru@redhat.com>

9 files changed, 43 insertions, 0 deletions

diff --git a/target/cris/crisv10-decode.h b/target/cris/crisv10-decode.h
index bdb4b6d..028179b 100644
--- a/target/cris/crisv10-decode.h
+++ b/target/cris/crisv10-decode.h
@@ -18,6 +18,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_CRIS_CRISV10_DECODE_H
+#define TARGET_CRIS_CRISV10_DECODE_H
+
 #define CRISV10_MODE_QIMMEDIATE  0
 #define CRISV10_MODE_REG         1
 #define CRISV10_MODE_INDIRECT    2
@@ -106,3 +109,4 @@
 #define CRISV10_IND_MOVEM_M_R    14
 #define CRISV10_IND_MOVEM_R_M    15
 
+#endif
diff --git a/target/cris/mmu.h b/target/cris/mmu.h
index 0217f47..9ab1642 100644
--- a/target/cris/mmu.h
+++ b/target/cris/mmu.h
@@ -1,3 +1,6 @@
+#ifndef TARGET_CRIS_MMU_H
+#define TARGET_CRIS_MMU_H
+
 #define CRIS_MMU_ERR_EXEC  0
 #define CRIS_MMU_ERR_READ  1
 #define CRIS_MMU_ERR_WRITE 2
@@ -15,3 +18,5 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid);
 int cris_mmu_translate(struct cris_mmu_result *res,
                        CPUCRISState *env, uint32_t vaddr,
                        int rw, int mmu_idx, int debug);
+
+#endif
diff --git a/target/microblaze/microblaze-decode.h b/target/microblaze/microblaze-decode.h
index 401319e..17b2f29 100644
--- a/target/microblaze/microblaze-decode.h
+++ b/target/microblaze/microblaze-decode.h
@@ -17,6 +17,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_MICROBLAZE_MICROBLAZE_DECODE_H
+#define TARGET_MICROBLAZE_MICROBLAZE_DECODE_H
+
 /* Convenient binary macros.  */
 #define HEX__(n) 0x##n##LU
 #define B8__(x) ((x&0x0000000FLU)?1:0) \
@@ -53,3 +56,4 @@
 
 #define DEC_STREAM  {B8(00010011), B8(00110111)}
 
+#endif
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index a4272b6..75e5301 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -17,6 +17,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_MICROBLAZE_MMU_H
+#define TARGET_MICROBLAZE_MMU_H
+
 #define MMU_R_PID    0
 #define MMU_R_ZPR    1
 #define MMU_R_TLBX   2
@@ -93,3 +96,5 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
 void mmu_init(struct microblaze_mmu *mmu);
+
+#endif
diff --git a/target/moxie/mmu.h b/target/moxie/mmu.h
index 284a44d..d80690f 100644
--- a/target/moxie/mmu.h
+++ b/target/moxie/mmu.h
@@ -1,3 +1,6 @@
+#ifndef TARGET_MOXIE_MMU_H
+#define TARGET_MOXIE_MMU_H
+
 #define MOXIE_MMU_ERR_EXEC  0
 #define MOXIE_MMU_ERR_READ  1
 #define MOXIE_MMU_ERR_WRITE 2
@@ -12,3 +15,5 @@ typedef struct {
 int moxie_mmu_translate(MoxieMMUResult *res,
                         CPUMoxieState *env, uint32_t vaddr,
                         int rw, int mmu_idx);
+
+#endif
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index dc9d53d..47450a3 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -1,5 +1,8 @@
 /* RISC-V ISA constants */
 
+#ifndef TARGET_RISCV_CPU_BITS_H
+#define TARGET_RISCV_CPU_BITS_H
+
 #define get_field(reg, mask) (((reg) & \
                  (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
@@ -527,3 +530,5 @@
 #define SIP_SSIP                           MIP_SSIP
 #define SIP_STIP                           MIP_STIP
 #define SIP_SEIP                           MIP_SEIP
+
+#endif
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index 52d380a..02afad6 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -1,3 +1,6 @@
+#ifndef TARGET_RISCV_CPU_USER_H
+#define TARGET_RISCV_CPU_USER_H
+
 #define xRA 1   /* return address (aka link register) */
 #define xSP 2   /* stack pointer */
 #define xGP 3   /* global pointer */
@@ -12,3 +15,5 @@
 #define xA6 16
 #define xA7 17  /* syscall number for RVI ABI */
 #define xT0 5   /* syscall number for RVE ABI */
+
+#endif
diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h
index 58baa1b..f8ad7d6 100644
--- a/target/riscv/instmap.h
+++ b/target/riscv/instmap.h
@@ -16,6 +16,9 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_RISCV_INSTMAP_H
+#define TARGET_RISCV_INSTMAP_H
+
 #define MASK_OP_MAJOR(op)  (op & 0x7F)
 enum {
     /* rv32i, rv64i, rv32m */
@@ -362,3 +365,5 @@ enum {
 #define GET_C_RS2(inst)             extract32(inst, 2, 5)
 #define GET_C_RS1S(inst)            (8 + extract32(inst, 7, 3))
 #define GET_C_RS2S(inst)            (8 + extract32(inst, 2, 3))
+
+#endif
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 40bc121..f7135f1 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -15,6 +15,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_TRICORE_TRICORE_OPCODES_H
+#define TARGET_TRICORE_TRICORE_OPCODES_H
+
 /*
  * Opcode Masks for Tricore
  * Format MASK_OP_InstrFormatName_Field
@@ -1467,3 +1470,5 @@ enum {
     OPC2_32_SYS_RESTORE                          = 0x0e,
     OPC2_32_SYS_FRET                             = 0x03,
 };
+
+#endif