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author | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-23 09:33:22 +0200 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-06-11 14:29:22 +0200 |
commit | e628387cf9a27a4895b00821313635fad4cfab43 (patch) | |
tree | 0ecd69f764e82907cde00e99e3c76832ad41a0f3 /target | |
parent | cc155f19717ced44d70df3cd5f149a5b9f9a13f1 (diff) | |
download | qemu-e628387cf9a27a4895b00821313635fad4cfab43.zip qemu-e628387cf9a27a4895b00821313635fad4cfab43.tar.gz qemu-e628387cf9a27a4895b00821313635fad4cfab43.tar.bz2 |
target/i386: put BLS* input in T1, use generic flag writeback
This makes for easier cpu_cc_* setup, and not using set_cc_op()
should come in handy if QEMU ever implements APX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/i386/tcg/decode-new.c.inc | 4 | ||||
-rw-r--r-- | target/i386/tcg/emit.c.inc | 24 |
2 files changed, 11 insertions, 17 deletions
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index e7d8802..380fb79 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -633,7 +633,7 @@ static const X86OpEntry opcodes_0F38_F0toFF[16][5] = { {}, }, [3] = { - X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)), + X86_OP_GROUP3(group17, B,y, None,None, E,y, vex13 cpuid(BMI1)), {}, {}, {}, @@ -2604,7 +2604,7 @@ static void disas_insn(DisasContext *s, CPUState *cpu) } /* - * Write back flags after last memory access. Some newer ALU instructions, as + * Write back flags after last memory access. Some older ALU instructions, as * well as SSE instructions, write flags in the gen_* function, but that can * cause incorrect tracking of CC_OP for instructions that write to both memory * and flags. diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2041ea9..a25b3df 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1272,40 +1272,34 @@ static void gen_BEXTR(DisasContext *s, X86DecodedInsn *decode) prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); } -/* BLSI do not have memory operands and can use set_cc_op. */ static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_neg_tl(s->T1, s->T0); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_neg_tl(s->T0, s->T1); tcg_gen_and_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } -/* BLSMSK do not have memory operands and can use set_cc_op. */ static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_subi_tl(s->T1, s->T0, 1); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_subi_tl(s->T0, s->T1, 1); tcg_gen_xor_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } -/* BLSR do not have memory operands and can use set_cc_op. */ static void gen_BLSR(DisasContext *s, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_subi_tl(s->T1, s->T0, 1); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_subi_tl(s->T0, s->T1, 1); tcg_gen_and_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode) |