aboutsummaryrefslogtreecommitdiff
path: root/target
diff options
context:
space:
mode:
authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-11-26 11:54:30 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-14 17:13:53 +0100
commitdd5697b2f90c3c6aa4a97b247aa70635914a6041 (patch)
tree965242f73874a96489637ec5e1e528662df20535 /target
parent9a7372e35491fc4c8f0bb20359dda87626bdf831 (diff)
downloadqemu-dd5697b2f90c3c6aa4a97b247aa70635914a6041.zip
qemu-dd5697b2f90c3c6aa4a97b247aa70635914a6041.tar.gz
qemu-dd5697b2f90c3c6aa4a97b247aa70635914a6041.tar.bz2
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
Diffstat (limited to 'target')
-rw-r--r--target/mips/mips32r6.decode5
-rw-r--r--target/mips/translate.c4
2 files changed, 5 insertions, 4 deletions
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index cb86877..0b5befc 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -20,6 +20,11 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 011111 ----- ----- ---------- 011001 # LWLE
+REMOVED 011111 ----- ----- ---------- 011010 # LWRE
+REMOVED 011111 ----- ----- ---------- 100001 # SWLE
+REMOVED 011111 ----- ----- ---------- 100010 # SWRE
+
REMOVED 100010 ----- ----- ---------------- # LWL
REMOVED 100110 ----- ----- ---------------- # LWR
REMOVED 101010 ----- ----- ---------------- # SWL
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d9d9952..ffe2839 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28121,8 +28121,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_LWLE:
case OPC_LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_LBUE:
case OPC_LHUE:
case OPC_LBE:
@@ -28134,8 +28132,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SWLE:
case OPC_SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_SBE:
case OPC_SHE:
case OPC_SWE: