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author | Richard Henderson <richard.henderson@linaro.org> | 2024-01-29 10:13:23 +1000 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2024-02-03 16:46:10 +1000 |
commit | db8b41941aabdfdc505b372ae8b8445581e96840 (patch) | |
tree | 2af5c7ee002f7b3d8701b4257b09e3a5972539be /target | |
parent | 498c7d78d3ef0346d3885842c505eb8d0ffb940e (diff) | |
download | qemu-db8b41941aabdfdc505b372ae8b8445581e96840.zip qemu-db8b41941aabdfdc505b372ae8b8445581e96840.tar.gz qemu-db8b41941aabdfdc505b372ae8b8445581e96840.tar.bz2 |
target/openrisc: Populate CPUClass.mmu_index
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/openrisc/cpu.c | 13 | ||||
-rw-r--r-- | target/openrisc/cpu.h | 10 |
2 files changed, 15 insertions, 8 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 477d49d..8670152 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUOpenRISCState *env = cpu_env(cs); + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return MMU_NOMMU_IDX; /* mmu is disabled */ +} + static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn = print_insn_or1k; @@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; + cc->mmu_index = openrisc_cpu_mmu_index; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->get_pc = openrisc_cpu_get_pc; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014..7dbed8d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - int ret = MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; + return openrisc_cpu_mmu_index(env_cpu(env), ifetch); } static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) |