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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-05-06 00:06:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:46 +1000 |
| commit | d52e94081e626b6b4b181dc7a6fc8f0b98e7d403 (patch) | |
| tree | 5238e2e98fe0de74d612ee039fb80b6c15922ee7 /target | |
| parent | 3a4a43e4e213a18d1ee4ed97090a5e86401c85bc (diff) | |
| download | qemu-d52e94081e626b6b4b181dc7a6fc8f0b98e7d403.zip qemu-d52e94081e626b6b4b181dc7a6fc8f0b98e7d403.tar.gz qemu-d52e94081e626b6b4b181dc7a6fc8f0b98e7d403.tar.bz2 | |
target/riscv: rvb: support and turn on B-extension from command line
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 4 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ee2523f..5702c53 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -489,6 +489,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -559,6 +562,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0c99c3..de9262c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -286,6 +286,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h; |