diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-07-09 16:06:21 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-18 10:59:46 +0100 |
| commit | d102058e795229f53a443a58d10d8b457e96acb4 (patch) | |
| tree | ea0004c3030c408ea28e908919831dc0269da3d0 /target | |
| parent | a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf (diff) | |
| download | qemu-d102058e795229f53a443a58d10d8b457e96acb4.zip qemu-d102058e795229f53a443a58d10d8b457e96acb4.tar.gz qemu-d102058e795229f53a443a58d10d8b457e96acb4.tar.bz2 | |
target/arm: Fix offsets for TTBCR
The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect
the offset to be for the complete TCR structure, not the offset
to the low 32-bits of a uint64_t. Using offsetoflow32 in this
case breaks big-endian hosts.
For TTBCR2, we do want the high 32-bits of a uint64_t.
Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32 argument to
clarify this.
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/187
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210709230621.938821-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 910ace4..0c07ca9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4106,8 +4106,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, .raw_writefn = vmsa_ttbcr_raw_write, - .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), - offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, + /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), + offsetof(CPUARMState, cp15.tcr_el[1])} }, REGINFO_SENTINEL }; @@ -4118,8 +4119,10 @@ static const ARMCPRegInfo ttbcr2_reginfo = { .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, - .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), - offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, + .bank_fieldoffsets = { + offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + }, }; static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |