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| author | Ilya Leoshkevich <iii@linux.ibm.com> | 2023-08-07 13:48:20 +0200 |
|---|---|---|
| committer | Thomas Huth <thuth@redhat.com> | 2023-08-31 19:10:01 +0200 |
| commit | c7f41e4f53c4763bf1e350723a560dc3bf46e04b (patch) | |
| tree | ddde8ff0dd51107385ed9d52ed5f8b546cbc6de1 /target | |
| parent | 17780edd81d27fcfdb7a802efc870a99788bd2fc (diff) | |
| download | qemu-c7f41e4f53c4763bf1e350723a560dc3bf46e04b.zip qemu-c7f41e4f53c4763bf1e350723a560dc3bf46e04b.tar.gz qemu-c7f41e4f53c4763bf1e350723a560dc3bf46e04b.tar.bz2 | |
target/s390x: Define TARGET_HAS_PRECISE_SMC
PoP (Sequence of Storage References -> Instruction Fetching) says:
... if a store that is conceptually earlier is
made by the same CPU using the same effective
address as that by which the instruction is subse-
quently fetched, the updated information is obtained ...
QEMU already has support for this in the common code; enable it for
s390x.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20230807114921.438881-1-iii@linux.ibm.com>
Acked-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/s390x/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index eb5b65b..304029e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -36,6 +36,8 @@ /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define TARGET_HAS_PRECISE_SMC + #define TARGET_INSN_START_EXTRA_WORDS 2 #define MMU_USER_IDX 0 |