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authorRichard Henderson <richard.henderson@linaro.org>2021-10-12 06:16:25 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-10-12 06:16:25 -0700
commitbfd9a76f9c143d450ab5545dedfa74364b39fc56 (patch)
tree221db58dcec3eb0c5b6e66640f718987c48326a6 /target
parent81d8537cb297d57b0897797f1329e4d755a0eaf4 (diff)
parent17888749ba0fb06694de5efe0b941f16a0fba6fa (diff)
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Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-2' into staging
Some testing and plugin updates: - don't override the test compiler when specified - split some multiarch tests by guest OS - add riscv64 docker image and cross-compile tests - drop release tarball test from Travis - skip check-patch on master repo - fix passing of TEST_TARGETS to cirrus - fix missing symbols in plugins - ensure s390x insn start ops precede plugin instrumentation - refactor plugin instruction boundary detection - update github repo lockdown - add a debian-native test image for multi-arch builds # gpg: Signature made Tue 12 Oct 2021 02:35:00 AM PDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] * remotes/stsquad/tags/pull-for-6.2-121021-2: tests/docker: add a debian-native image and make available .github: move repo lockdown to the v2 configuration accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is valid target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start plugins/: Add missing functions to symbol list gitlab: fix passing of TEST_TARGETS env to cirrus gitlab: skip the check-patch job on the upstream repo travis.yml: Remove the "Release tarball" job gitlab: Add cross-riscv64-system, cross-riscv64-user tests/docker: promote debian-riscv64-cross to a full image tests/tcg: move some multiarch files and make conditional tests/tcg/sha1: remove endian include configure: don't override the selected host test compiler if defined Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/s390x/tcg/translate.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index f284870..a2d6fa5 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -138,6 +138,7 @@ struct DisasFields {
struct DisasContext {
DisasContextBase base;
const DisasInsn *insn;
+ TCGOp *insn_start;
DisasFields fields;
uint64_t ex_value;
/*
@@ -6380,8 +6381,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
/* Search for the insn in the table. */
insn = extract_insn(env, s);
- /* Emit insn_start now that we know the ILEN. */
- tcg_gen_insn_start(s->base.pc_next, s->cc_op, s->ilen);
+ /* Update insn_start now that we know the ILEN. */
+ tcg_set_insn_start_param(s->insn_start, 2, s->ilen);
/* Not found means unimplemented/illegal opcode. */
if (insn == NULL) {
@@ -6552,6 +6553,11 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ /* Delay the set of ilen until we've read the insn. */
+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
+ dc->insn_start = tcg_last_op();
}
static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)