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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2020-07-01 23:25:34 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-02 09:19:33 -0700 |
| commit | bba718200b2d2aac6ab5031817f7125571c983a1 (patch) | |
| tree | f123d23a0c4cfa5c4e0111058a28834f32471b59 /target | |
| parent | fe5c9ab1fc185e96bf7e034954127429ca74d386 (diff) | |
| download | qemu-bba718200b2d2aac6ab5031817f7125571c983a1.zip qemu-bba718200b2d2aac6ab5031817f7125571c983a1.tar.gz qemu-bba718200b2d2aac6ab5031817f7125571c983a1.tar.bz2 | |
target/riscv: vector wideing integer reduction instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-47-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/helper.h | 7 | ||||
| -rw-r--r-- | target/riscv/insn32.decode | 2 | ||||
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.inc.c | 4 | ||||
| -rw-r--r-- | target/riscv/vector_helper.c | 11 |
4 files changed, 24 insertions, 0 deletions
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a7fe444..1c1277c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1072,3 +1072,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 878eeec..b78fd8b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -539,6 +539,8 @@ vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm +vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm +vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index b4e3f90..91fc1fd 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2342,3 +2342,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check) GEN_OPIVV_TRANS(vredand_vs, reduction_check) GEN_OPIVV_TRANS(vredor_vs, reduction_check) GEN_OPIVV_TRANS(vredxor_vs, reduction_check) + +/* Vector Widening Integer Reduction Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 41564b3..72b812c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4406,3 +4406,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) + +/* Vector Widening Integer Reduction Instructions */ +/* signed sum reduction into double-width accumulator */ +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) + +/* Unsigned sum reduction into double-width accumulator */ +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) |