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authorMichael Clark <mjc@sifive.com>2018-03-06 10:33:31 +1300
committerMichael Clark <mjc@sifive.com>2018-05-06 10:39:38 +1200
commitb8643bd6084be1787a6dc8768a7a1983921fc945 (patch)
tree89d854a5e83b6aad4e7656604ccad89a29d169a5 /target
parent1d1ee55274860bfcc511d50d83c84394c2685ba8 (diff)
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RISC-V: No traps on writes to misa,minstret,mcycle
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/op_helper.c25
1 files changed, 13 insertions, 12 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index af0c52a..3abf524 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
break;
}
case CSR_MINSTRET:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
- goto do_illegal;
+ /* minstret is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLE:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
- goto do_illegal;
+ /* mcycle is WARL so unsupported writes are ignored */
+ break;
+#if defined(TARGET_RISCV32)
case CSR_MINSTRETH:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
- goto do_illegal;
+ /* minstreth is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLEH:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
- goto do_illegal;
+ /* mcycleh is WARL so unsupported writes are ignored */
+ break;
+#endif
case CSR_MUCOUNTEREN:
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
env->scounteren = val_to_write;
@@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
case CSR_MBADADDR:
env->mbadaddr = val_to_write;
break;
- case CSR_MISA: {
- qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
- goto do_illegal;
- }
+ case CSR_MISA:
+ /* misa is WARL so unsupported writes are ignored */
+ break;
case CSR_PMPCFG0:
case CSR_PMPCFG1:
case CSR_PMPCFG2: