diff options
| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:55 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | b1675eeb3e6e38b042a23a9647559c9c548c733d (patch) | |
| tree | bc5b0e5aa6ee899d84d2f2d63c172f315f618c3c /target | |
| parent | 18d6d89efc60f1c030c4a8a22816d2d911ece105 (diff) | |
| download | qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.zip qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.tar.gz qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.tar.bz2 | |
target/riscv: Implement mcountinhibit CSR
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_bits.h | 4 | ||||
| -rw-r--r-- | target/riscv/csr.c | 25 | ||||
| -rw-r--r-- | target/riscv/machine.c | 1 |
4 files changed, 32 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ffee54e..0a916db 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,6 +275,8 @@ struct CPUArchState { target_ulong scounteren; target_ulong mcounteren; + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20..b3f7fa7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -367,6 +367,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b4a8e15..94d39a4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1475,6 +1475,28 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val = env->mcountinhibit; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit = val; + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -3745,6 +3767,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero }, [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero }, + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, + write_mcountinhibit }, + [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 2a437b2..87cd55b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -330,6 +330,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), |