diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2021-06-01 16:35:17 -0300 |
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committer | David Gibson <david@gibson.dropbear.id.au> | 2021-06-03 18:10:31 +1000 |
commit | 99082815f17f40d3527b281c7e3e6e5556fad8f1 (patch) | |
tree | 54111670b5d1440ff8abf476774fbed15f3c776d /target | |
parent | 64a0f6448c6b4454c35e5a73e8be7dee0f852ba5 (diff) | |
download | qemu-99082815f17f40d3527b281c7e3e6e5556fad8f1.zip qemu-99082815f17f40d3527b281c7e3e6e5556fad8f1.tar.gz qemu-99082815f17f40d3527b281c7e3e6e5556fad8f1.tar.bz2 |
target/ppc: Add infrastructure for prefixed insns
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
-rw-r--r-- | target/ppc/cpu.h | 1 | ||||
-rw-r--r-- | target/ppc/insn32.decode | 18 | ||||
-rw-r--r-- | target/ppc/insn64.decode | 18 | ||||
-rw-r--r-- | target/ppc/meson.build | 9 | ||||
-rw-r--r-- | target/ppc/translate.c | 37 | ||||
-rw-r--r-- | target/ppc/translate/fixedpoint-impl.c.inc | 18 |
6 files changed, 95 insertions, 6 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b7ae490..b4de0db 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -144,6 +144,7 @@ enum { POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ /* Exception subtypes for POWERPC_EXCP_PROGRAM */ /* FP exceptions */ POWERPC_EXCP_FP = 0x10, diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode new file mode 100644 index 0000000..a3a8ae0 --- /dev/null +++ b/target/ppc/insn32.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 32-bit insns (opcode space 0) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see <http://www.gnu.org/licenses/>. +# diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode new file mode 100644 index 0000000..a38b1f8 --- /dev/null +++ b/target/ppc/insn64.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see <http://www.gnu.org/licenses/>. +# diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a6a53a8..a4f18ff 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -20,6 +20,15 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( ppc_ss.add(libdecnumber) +gen = [ + decodetree.process('insn32.decode', + extra_args: '--static-decode=decode_insn32'), + decodetree.process('insn64.decode', + extra_args: ['--static-decode=decode_insn64', + '--insnwidth=64']), +] +ppc_ss.add(gen) + ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d2c9fd9..f3f464c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7690,6 +7690,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +#include "decode-insn32.c.inc" +#include "decode-insn64.c.inc" +#include "translate/fixedpoint-impl.c.inc" + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" @@ -8850,11 +8854,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, return true; } +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + return opc1(insn) == 1; +} + static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = cs->env_ptr; + target_ulong pc; uint32_t insn; bool ok; @@ -8862,18 +8873,32 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); - ctx->cia = ctx->base.pc_next; - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); - ctx->base.pc_next += 4; + ctx->cia = pc = ctx->base.pc_next; + insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; - ok = decode_legacy(cpu, ctx, insn); + if (!is_prefix_insn(ctx, insn)) { + ok = (decode_insn32(ctx, insn) || + decode_legacy(cpu, ctx, insn)); + } else if ((pc & 63) == 0) { + /* + * Power v3.1, section 1.9 Exceptions: + * attempt to execute a prefixed instruction that crosses a + * 64-byte address boundary (system alignment error). + */ + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); + ok = true; + } else { + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); + } if (!ok) { gen_invalid(ctx); } /* End the TB when crossing a page boundary. */ - if (ctx->base.is_jmp == DISAS_NEXT && - !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) { + if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { ctx->base.is_jmp = DISAS_TOO_MANY; } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc new file mode 100644 index 0000000..be75085 --- /dev/null +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,18 @@ +/* + * Power ISA decode for Fixed-Point Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ |