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author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-26 11:14:48 -1000 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-13 06:44:37 -0700 |
commit | 905a83dedf62a230adbfb7d66b9cf20ab044ab68 (patch) | |
tree | dc19bcaf84232a4689b45ae698808a1baa7d7618 /target | |
parent | 950b91be9807c93a3b7cd741257e369535b4de1c (diff) | |
download | qemu-905a83dedf62a230adbfb7d66b9cf20ab044ab68.zip qemu-905a83dedf62a230adbfb7d66b9cf20ab044ab68.tar.gz qemu-905a83dedf62a230adbfb7d66b9cf20ab044ab68.tar.bz2 |
tcg/sparc: Avoid tcg_const_tl in gen_edge
Push tcg_constant_tl into the shift argument directly.
Since t1 no longer exists as a temp, replace with lo1,
whose last use was just above.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/sparc/translate.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5ee2933..137bdc5 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, int width, bool cc, bool left) { - TCGv lo1, lo2, t1, t2; + TCGv lo1, lo2; uint64_t amask, tabl, tabr; int shift, imask, omask; @@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_gen_shli_tl(lo1, lo1, shift); tcg_gen_shli_tl(lo2, lo2, shift); - t1 = tcg_const_tl(tabl); - t2 = tcg_const_tl(tabr); - tcg_gen_shr_tl(lo1, t1, lo1); - tcg_gen_shr_tl(lo2, t2, lo2); + tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); + tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); tcg_gen_andi_tl(dst, lo1, omask); tcg_gen_andi_tl(lo2, lo2, omask); @@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, lo2 |= -(s1 == s2) dst &= lo2 */ - tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); - tcg_gen_neg_tl(t1, t1); - tcg_gen_or_tl(lo2, lo2, t1); + tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2); + tcg_gen_neg_tl(lo1, lo1); + tcg_gen_or_tl(lo2, lo2, lo1); tcg_gen_and_tl(dst, dst, lo2); } |