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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-12 11:57:50 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-17 11:13:15 +0200 |
| commit | 8dadffc01700f79fd66db972fff3a93a594715ee (patch) | |
| tree | db238390da1d3207854d153ca5c016ec819e0caa /target | |
| parent | 62f8f2603da7fbcc481489d2903558001a896cad (diff) | |
| download | qemu-8dadffc01700f79fd66db972fff3a93a594715ee.zip qemu-8dadffc01700f79fd66db972fff3a93a594715ee.tar.gz qemu-8dadffc01700f79fd66db972fff3a93a594715ee.tar.bz2 | |
target/mips/cp0_timer: Document TIMER_PERIOD origin
TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/cp0_timer.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5194c96..6fec5fe 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -27,7 +27,17 @@ #include "sysemu/kvm.h" #include "internal.h" -#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ +/* + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz + * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2). + * + * TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz + * + * TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns + */ +#define CPU_FREQ_HZ_DEFAULT 200000000 +#define CP0_COUNT_RATE_DEFAULT 2 +#define TIMER_PERIOD 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) |