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author | Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> | 2017-07-31 19:01:35 +0300 |
---|---|---|
committer | Stefan Hajnoczi <stefanha@redhat.com> | 2017-08-01 12:13:07 +0100 |
commit | 8908eb1a4aaf6b6573de3c44dfdaac6049061c02 (patch) | |
tree | d1b5bf8364b89a6723c6a59a1198ebabd78a03d6 /target | |
parent | c3e5875afc0f93315470dfa5f31251fb9546c267 (diff) | |
download | qemu-8908eb1a4aaf6b6573de3c44dfdaac6049061c02.zip qemu-8908eb1a4aaf6b6573de3c44dfdaac6049061c02.tar.gz qemu-8908eb1a4aaf6b6573de3c44dfdaac6049061c02.tar.bz2 |
trace-events: fix code style: print 0x before hex numbers
The only exception are groups of numers separated by symbols
'.', ' ', ':', '/', like 'ab.09.7d'.
This patch is made by the following:
> find . -name trace-events | xargs python script.py
where script.py is the following python script:
=========================
#!/usr/bin/env python
import sys
import re
import fileinput
rhex = '%[-+ *.0-9]*(?:[hljztL]|ll|hh)?(?:x|X|"\s*PRI[xX][^"]*"?)'
rgroup = re.compile('((?:' + rhex + '[.:/ ])+' + rhex + ')')
rbad = re.compile('(?<!0x)' + rhex)
files = sys.argv[1:]
for fname in files:
for line in fileinput.input(fname, inplace=True):
arr = re.split(rgroup, line)
for i in range(0, len(arr), 2):
arr[i] = re.sub(rbad, '0x\g<0>', arr[i])
sys.stdout.write(''.join(arr))
=========================
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20170731160135.12101-5-vsementsov@virtuozzo.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/arm/trace-events | 10 | ||||
-rw-r--r-- | target/s390x/trace-events | 2 | ||||
-rw-r--r-- | target/sparc/trace-events | 30 |
3 files changed, 21 insertions, 21 deletions
diff --git a/target/arm/trace-events b/target/arm/trace-events index c4fcda5..9e37131 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -1,10 +1,10 @@ # See docs/devel/tracing.txt for syntax documentation. # target/arm/helper.c -arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: timer %d irqstate %d next tick %" PRIx64 +arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: timer %d irqstate %d next tick 0x%" PRIx64 arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer disabled" -arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value %" PRIx64 -arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value %" PRIx64 -arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value %" PRIx64 +arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value 0x%" PRIx64 +arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%" PRIx64 +arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64 arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d" -arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value %" PRIx64 +arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 diff --git a/target/s390x/trace-events b/target/s390x/trace-events index 852a248..4d871f5 100644 --- a/target/s390x/trace-events +++ b/target/s390x/trace-events @@ -8,7 +8,7 @@ set_skeys_nonzero(int rc) "SKEY: Call to set_skeys unexpectedly returned %d" ioinst(const char *insn) "IOINST: %s" ioinst_sch_id(const char *insn, int cssid, int ssid, int schid) "IOINST: %s (%x.%x.%04x)" ioinst_chp_id(const char *insn, int cssid, int chpid) "IOINST: %s (%x.%02x)" -ioinst_chsc_cmd(uint16_t cmd, uint16_t len) "IOINST: chsc command %04x, len %04x" +ioinst_chsc_cmd(uint16_t cmd, uint16_t len) "IOINST: chsc command 0x%04x, len 0x%04x" # target/s390x/kvm.c kvm_enable_cmma(int rc) "CMMA: enabling with result code %d" diff --git a/target/sparc/trace-events b/target/sparc/trace-events index 8d1ed1b..764b1e5 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -1,28 +1,28 @@ # See docs/devel/tracing.txt for syntax documentation. # target/sparc/mmu_helper.c -mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" -mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" -mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at %"PRIx64" context %"PRIx64 -mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at %"PRIx64" context %"PRIx64 -mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context %"PRIx64 -mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 -mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 -mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64 +mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at 0x%"PRIx64" context 0x%"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at 0x%"PRIx64" context 0x%"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at 0x%"PRIx64" context 0x%"PRIx64 +mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at 0x%"PRIx64" context 0x%"PRIx64 +mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at 0x%"PRIx64" context 0x%"PRIx64 +mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64 +mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64 +mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64 # target/sparc/int64_helper.c -int_helper_set_softint(uint32_t softint) "new %08x" -int_helper_clear_softint(uint32_t softint) "new %08x" -int_helper_write_softint(uint32_t softint) "new %08x" +int_helper_set_softint(uint32_t softint) "new 0x%08x" +int_helper_clear_softint(uint32_t softint) "new 0x%08x" +int_helper_write_softint(uint32_t softint) "new 0x%08x" # target/sparc/int32_helper.c int_helper_icache_freeze(void) "Instruction cache: freeze" int_helper_dcache_freeze(void) "Data cache: freeze" # target/sparc/win_helper.c -win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=%x" -win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=%x new=%x" -win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=%x (unchanged)" -win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=%x new=%x" +win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x" +win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x" +win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=0x%x (unchanged)" +win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=0x%x new=0x%x" win_helper_done(uint32_t tl) "tl=%d" win_helper_retry(uint32_t tl) "tl=%d" |