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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 16:49:15 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 86d0c457396b1a789fe2740f7bd8d476ea426298 (patch) | |
| tree | 3686d6412105f9001154d72b264169300da395c6 /target | |
| parent | ea7b5d5af6c3f994b10caa80c7f41964678eb2bb (diff) | |
| download | qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.zip qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.tar.gz qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.tar.bz2 | |
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 10f3bab..ddacb85 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -998,6 +998,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + bool write_gva = false; uint64_t s; /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1006,7 +1007,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg = async ? env->mideleg : env->medeleg; - bool write_tval = false; target_ulong tval = 0; target_ulong htval = 0; target_ulong mtval2 = 0; @@ -1035,7 +1035,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: - write_tval = true; + write_gva = true; tval = env->badaddr; break; default: @@ -1072,18 +1072,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg = async ? env->hideleg : env->hedeleg; - if (env->two_stage_lookup && write_tval) { - /* - * If we are writing a guest virtual address to stval, set - * this to 1. If we are trapping to VS we will set this to 0 - * later. - */ - env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); - } else { - /* For other HS-mode traps, we set this to 0. */ - env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); - } - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* @@ -1094,7 +1082,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause == IRQ_VS_EXT) { cause = cause - 1; } - env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); + write_gva = false; } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -1103,6 +1091,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->hstatus = set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); + htval = env->guest_phys_fault_addr; riscv_cpu_set_virt_enabled(env, 0); @@ -1110,7 +1099,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trap into HS mode */ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); htval = env->guest_phys_fault_addr; + write_gva = false; } + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); } s = env->mstatus; |