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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-20 19:49:40 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:34 +0200 |
| commit | 84c2fdc397b6609d1cef76aec2f1367139d1372e (patch) | |
| tree | 026a408aafdf5dfe159a336eb3ed22cb76d94f44 /target | |
| parent | bcad139192b0101e3d7ef593144c314bed4cb8c2 (diff) | |
| download | qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.zip qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.tar.gz qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.tar.bz2 | |
target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 71fa5ec..5dad75c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20957,6 +20957,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_ld(ctx, OPC_LHUE, rt, rs, s); break; case NM_CACHEE: + check_eva(ctx); + check_cp0_enabled(ctx); check_nms_dl_il_sl_tl_l2c(ctx); gen_cache_operation(ctx, rt, rs, s); break; @@ -24530,11 +24532,11 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); return; case OPC_CACHEE: + check_eva(ctx); check_cp0_enabled(ctx); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } - /* Treat as NOP. */ return; case OPC_PREFE: check_cp0_enabled(ctx); |