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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-13 14:47:47 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-07-11 22:29:54 +0200 |
| commit | 80ad6303577612451d56c84d079a8c5b7f21412d (patch) | |
| tree | b7aacff642f6b05efd259fc7e5460a816c3a9d7f /target | |
| parent | aaaa82a9f9975c59b72debb22bc92b8e1ab4ab10 (diff) | |
| download | qemu-80ad6303577612451d56c84d079a8c5b7f21412d.zip qemu-80ad6303577612451d56c84d079a8c5b7f21412d.tar.gz qemu-80ad6303577612451d56c84d079a8c5b7f21412d.tar.bz2 | |
target/mips/tx79: Introduce SQ opcode (Store Quadword)
Introduce the SQ opcode (Store Quadword).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-27-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/tcg/tx79.decode | 1 | ||||
| -rw-r--r-- | target/mips/tcg/tx79_translate.c | 27 |
2 files changed, 28 insertions, 0 deletions
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 0af5c6d..03a25a5 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -70,3 +70,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd # SPECIAL LQ 011110 ..... ..... ................ @ldst +SQ 011111 ..... ..... ................ @ldst diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index d9193b4..395d6af 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -369,6 +369,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } +static bool trans_SQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv addr = tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower half */ + gen_load_gpr(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + /* Upper half */ + tcg_gen_addi_i64(addr, addr, 8); + gen_load_gpr_hi(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(addr); + tcg_temp_free(t0); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- |