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| author | Taylor Simpson <tsimpson@quicinc.com> | 2021-08-03 13:36:42 -0500 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2021-11-03 16:01:34 -0500 |
| commit | 7f4808ec99189689c07ead85521b381b1562daf3 (patch) | |
| tree | 95ea5287b037f901f8d63066176890344bedf65b /target | |
| parent | 2c8ffa8f823e7f1a103971f48ae6c7a1eaf0be72 (diff) | |
| download | qemu-7f4808ec99189689c07ead85521b381b1562daf3.zip qemu-7f4808ec99189689c07ead85521b381b1562daf3.tar.gz qemu-7f4808ec99189689c07ead85521b381b1562daf3.tar.bz2 | |
Hexagon HVX (target/hexagon) helper overrides - vector logical ops
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/hexagon/gen_tcg_hvx.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index f548404..f53a7f2 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -361,4 +361,46 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \ sizeof(MMVector), sizeof(MMVector)) +/* Vector logical ops */ +#define fGEN_TCG_V6_vxor(SHORTCODE) \ + tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ + sizeof(MMVector), sizeof(MMVector)) + +#define fGEN_TCG_V6_vand(SHORTCODE) \ + tcg_gen_gvec_and(MO_64, VdV_off, VuV_off, VvV_off, \ + sizeof(MMVector), sizeof(MMVector)) + +#define fGEN_TCG_V6_vor(SHORTCODE) \ + tcg_gen_gvec_or(MO_64, VdV_off, VuV_off, VvV_off, \ + sizeof(MMVector), sizeof(MMVector)) + +#define fGEN_TCG_V6_vnot(SHORTCODE) \ + tcg_gen_gvec_not(MO_64, VdV_off, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) + +/* Q register logical ops */ +#define fGEN_TCG_V6_pred_or(SHORTCODE) \ + tcg_gen_gvec_or(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_and(SHORTCODE) \ + tcg_gen_gvec_and(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_xor(SHORTCODE) \ + tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_or_n(SHORTCODE) \ + tcg_gen_gvec_orc(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_and_n(SHORTCODE) \ + tcg_gen_gvec_andc(MO_64, QdV_off, QsV_off, QtV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + +#define fGEN_TCG_V6_pred_not(SHORTCODE) \ + tcg_gen_gvec_not(MO_64, QdV_off, QsV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) + #endif |