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authorPeter Maydell <peter.maydell@linaro.org>2022-08-22 15:12:30 +0100
committerRichard Henderson <richard.henderson@linaro.org>2022-09-13 17:18:21 +0100
commit7d7fb11615809839ff858328134c6a0abad27ea4 (patch)
treeccf4d72fe3c93f6cb8fe012a1063c6eb451efa96 /target
parent870ab98bee4312caf0ced42999e295f741aba853 (diff)
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target/riscv: Honour -semihosting-config userspace=on and enable=on
The riscv target incorrectly enabled semihosting always, whether the user asked for it or not. Call semihosting_enabled() passing the correct value to the is_userspace argument, which fixes this and also handles the userspace=on argument. Because we do this at translate time, we no longer need to check the privilege level in riscv_cpu_do_interrupt(). Note that this is a behaviour change: we used to default to semihosting being enabled, and now the user must pass "-semihosting-config enable=on" if they want it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220822141230.3658237-8-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu_helper.c9
-rw-r--r--target/riscv/insn_trans/trans_privileged.c.inc3
-rw-r--r--target/riscv/translate.c1
3 files changed, 6 insertions, 7 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 67e4c0e..278d163 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1589,12 +1589,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong mtval2 = 0;
if (cause == RISCV_EXCP_SEMIHOST) {
- if (env->priv >= PRV_S) {
- do_common_semihosting(cs);
- env->pc += 4;
- return;
- }
- cause = RISCV_EXCP_BREAKPOINT;
+ do_common_semihosting(cs);
+ env->pc += 4;
+ return;
}
if (!async) {
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 46f96ad..3281408 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -52,7 +52,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
* that no exception will be raised when fetching them.
*/
- if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
+ if (semihosting_enabled(ctx->mem_idx < PRV_S) &&
+ (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
pre = opcode_at(&ctx->base, pre_addr);
ebreak = opcode_at(&ctx->base, ebreak_addr);
post = opcode_at(&ctx->base, post_addr);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8925a44..db123da 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -28,6 +28,7 @@
#include "exec/translator.h"
#include "exec/log.h"
+#include "semihosting/semihost.h"
#include "instmap.h"
#include "internals.h"