diff options
author | Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> | 2022-06-20 15:05:21 +0300 |
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committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-07-12 22:30:09 +0200 |
commit | 72d680e4083a75c55d89c55f799cbe870ebbc7a5 (patch) | |
tree | 6e574cbcda3a178b8b3d732dfe7d2a0d34228fae /target | |
parent | 8e3d85d36b77f11ad7bded3a2d48c1f0cc334f82 (diff) | |
download | qemu-72d680e4083a75c55d89c55f799cbe870ebbc7a5.zip qemu-72d680e4083a75c55d89c55f799cbe870ebbc7a5.tar.gz qemu-72d680e4083a75c55d89c55f799cbe870ebbc7a5.tar.bz2 |
target/mips: introduce decodetree structure for Cavium Octeon extension
This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/mips/mips-defs.h | 1 | ||||
-rw-r--r-- | target/mips/tcg/meson.build | 2 | ||||
-rw-r--r-- | target/mips/tcg/octeon.decode | 6 | ||||
-rw-r--r-- | target/mips/tcg/octeon_translate.c | 16 | ||||
-rw-r--r-- | target/mips/tcg/translate.c | 5 | ||||
-rw-r--r-- | target/mips/tcg/translate.h | 1 |
6 files changed, 31 insertions, 0 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0a12d98..a6cebe0 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -42,6 +42,7 @@ #define INSN_LOONGSON2E 0x0000040000000000ULL #define INSN_LOONGSON2F 0x0000080000000000ULL #define INSN_LOONGSON3A 0x0000100000000000ULL +#define INSN_OCTEON 0x0000200000000000ULL /* * bits 52-63: vendor-specific ASEs */ diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 9800377..7ee969e 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -3,6 +3,7 @@ gen = [ decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), + decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'), ] mips_ss.add(gen) @@ -24,6 +25,7 @@ mips_ss.add(files( )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', + 'octeon_translate.c', ), if_false: files( 'mxu_translate.c', )) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode new file mode 100644 index 0000000..b21c735 --- /dev/null +++ b/target/mips/tcg/octeon.decode @@ -0,0 +1,6 @@ +# Octeon Architecture Module instruction set +# +# Copyright (C) 2022 Pavel Dovgalyuk +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c new file mode 100644 index 0000000..8b5eb1a --- /dev/null +++ b/target/mips/tcg/octeon_translate.c @@ -0,0 +1,16 @@ +/* + * Octeon-specific instructions translation routines + * + * Copyright (c) 2022 Pavel Dovgalyuk + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-octeon.c.inc" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d9d7692..1f6a779 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15955,6 +15955,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { return; } +#if defined(TARGET_MIPS64) + if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { + return; + } +#endif /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 9997fe2..5505322 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); +bool decode_ext_octeon(DisasContext *ctx, uint32_t insn); #endif bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); |