diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2024-05-27 01:12:54 +0200 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:51:34 +1000 |
| commit | 719a1da19ee67cfd3ef5b50f778d0204daaeb0b2 (patch) | |
| tree | c095160b94a3059a40518e8fc1fa3c119d6b90c9 /target | |
| parent | cab21e2ecb917abec597a184fd44d479b4bb1e66 (diff) | |
| download | qemu-719a1da19ee67cfd3ef5b50f778d0204daaeb0b2.zip qemu-719a1da19ee67cfd3ef5b50f778d0204daaeb0b2.tar.gz qemu-719a1da19ee67cfd3ef5b50f778d0204daaeb0b2.tar.bz2 | |
target/ppc: Add function to get protection key for hash32 MMU
Add a function to get key bit from SR and use it instead of open coded
version.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/mmu-hash32.c | 9 | ||||
| -rw-r--r-- | target/ppc/mmu-hash32.h | 5 | ||||
| -rw-r--r-- | target/ppc/mmu_common.c | 3 |
3 files changed, 12 insertions, 5 deletions
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8a446c8..9355944 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -42,7 +42,7 @@ static int ppc_hash32_pte_prot(int mmu_idx, { unsigned pp, key; - key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); + key = ppc_hash32_key(mmuidx_pr(mmu_idx), sr); pp = pte.pte1 & HPTE32_R_PP; return ppc_hash32_prot(key, pp, !!(sr & SR32_NX)); @@ -145,7 +145,6 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - int key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); @@ -206,7 +205,11 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, cpu_abort(cs, "ERROR: insn should not need address translation\n"); } - *prot = key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { + *prot = PAGE_READ | PAGE_WRITE; + } else { + *prot = PAGE_READ; + } if (check_prot_access_type(*prot, access_type)) { *raddr = eaddr; return true; diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index bc4eedb..5902cf8 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -102,6 +102,11 @@ static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu, stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); } +static inline bool ppc_hash32_key(bool pr, target_ulong sr) +{ + return pr ? (sr & SR32_KP) : (sr & SR32_KS); +} + static inline int ppc_hash32_prot(bool key, int pp, bool nx) { int prot; diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 339df37..1ed2f45 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -310,8 +310,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, pr = FIELD_EX64(env->msr, MSR, PR); sr = env->sr[eaddr >> 28]; - ctx->key = (((sr & 0x20000000) && pr) || - ((sr & 0x40000000) && !pr)) ? 1 : 0; + ctx->key = ppc_hash32_key(pr, sr); ds = sr & SR32_T; nx = sr & SR32_NX; vsid = sr & SR32_VSID; |