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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-24 18:03:52 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:44 +0100 |
| commit | 64ea60869be0fc80e32055912fe3c1a55290231c (patch) | |
| tree | 00fcdcf89f4022dc18a083ed016cd62f3e4fcfb6 /target | |
| parent | 25fa6f8341f4dda26f43182090ec9cf9fd8ee7ce (diff) | |
| download | qemu-64ea60869be0fc80e32055912fe3c1a55290231c.zip qemu-64ea60869be0fc80e32055912fe3c1a55290231c.tar.gz qemu-64ea60869be0fc80e32055912fe3c1a55290231c.tar.bz2 | |
target/arm: Fix decode for VDOT (indexed)
We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm. Remove the incorrect
name and remove the incorrect decode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/neon-shared.decode | 4 | ||||
| -rw-r--r-- | target/arm/translate-neon.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index ca0c699..facb621 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -61,8 +61,8 @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0 -VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ - vm=%vm_dp vn=%vn_dp vd=%vd_dp +VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 vm:4 \ + vn=%vn_dp vd=%vd_dp %vfml_scalar_q0_rm 0:3 5:1 %vfml_scalar_q1_index 5:1 3:1 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 14a9d0d..9f7a88a 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -348,7 +348,7 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a) opr_sz = (1 + a->q) * 8; tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->rm), + vfp_reg_offset(1, a->vm), vfp_reg_offset(1, a->vd), opr_sz, opr_sz, a->index, fn_gvec); return true; |