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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-07-16 11:30:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-07-18 13:49:28 +0100 |
| commit | 5669d26ec614b3f4c56cf1489b9095ed327938b1 (patch) | |
| tree | e34c06cec3f1e99b1c13308442c2d4f8754ad09d /target | |
| parent | d74ec4d7dda6322bcc51d1b13ccbd993d3574795 (diff) | |
| download | qemu-5669d26ec614b3f4c56cf1489b9095ed327938b1.zip qemu-5669d26ec614b3f4c56cf1489b9095ed327938b1.tar.gz qemu-5669d26ec614b3f4c56cf1489b9095ed327938b1.tar.bz2 | |
target/arm: Fix handling of LDAPR/STLR with negative offset
When we converted the LDAPR/STLR instructions to decodetree we
accidentally introduced a regression where the offset is negative.
The 9-bit immediate field is signed, and the old hand decoder
correctly used sextract32() to get it out of the insn word,
but the ldapr_stlr_i pattern in the decode file used "imm:9"
instead of "imm:s9", so it treated the field as unsigned.
Fix the pattern to treat the field as a signed immediate.
Cc: qemu-stable@nongnu.org
Fixes: 2521b6073b7 ("target/arm: Convert LDAPR/STLR (imm) to decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2419
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240709134504.3500007-2-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/tcg/a64.decode | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 2922de7..62df4c4 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -520,7 +520,7 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm &ldapr_stlr_i rn rt imm sz sign ext -@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i +@ldapr_stlr_i .. ...... .. . imm:s9 .. rn:5 rt:5 &ldapr_stlr_i STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 |