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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:44 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:44 +0000 |
| commit | 4f61106614410945b1d1c93081544ad5b13044fc (patch) | |
| tree | 63f7cbd9211381fea1971911c025316361f83241 /target | |
| parent | 9c72b68ad746a51f63822cffab4d144b5957823a (diff) | |
| download | qemu-4f61106614410945b1d1c93081544ad5b13044fc.zip qemu-4f61106614410945b1d1c93081544ad5b13044fc.tar.gz qemu-4f61106614410945b1d1c93081544ad5b13044fc.tar.bz2 | |
target/arm/translate-a64: Don't underdecode add/sub extended register
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-a64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2cade64..94907f0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4201,6 +4201,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) int imm3 = extract32(insn, 10, 3); int option = extract32(insn, 13, 3); int rm = extract32(insn, 16, 5); + int opt = extract32(insn, 22, 2); bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool sf = extract32(insn, 31, 1); @@ -4209,7 +4210,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) TCGv_i64 tcg_rd; TCGv_i64 tcg_result; - if (imm3 > 4) { + if (imm3 > 4 || opt != 0) { unallocated_encoding(s); return; } |