diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2022-03-16 17:46:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 11:19:19 +0000 |
| commit | 4a7319b750d2a465c9697fb0c72584c5d4e9073a (patch) | |
| tree | ce11757a63cdccb46d2ba8f99e59b4a64dc8d887 /target | |
| parent | c28d4b8656c836b5b166b35e4c48ff26d9405b59 (diff) | |
| download | qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.zip qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.gz qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.bz2 | |
target/arm: Make rvbar settable after realize
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 12 | ||||
| -rw-r--r-- | target/arm/cpu.h | 3 | ||||
| -rw-r--r-- | target/arm/helper.c | 10 |
3 files changed, 16 insertions, 9 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 498fb9f..5d4ca7a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -236,7 +236,10 @@ static void arm_cpu_reset(DeviceState *dev) } else { env->pstate = PSTATE_MODE_EL1h; } - env->pc = cpu->rvbar; + + /* Sample rvbar at reset. */ + env->cp15.rvbar = cpu->rvbar_prop; + env->pc = env->cp15.rvbar; #endif } else { #if defined(CONFIG_USER_ONLY) @@ -1135,9 +1138,6 @@ static Property arm_cpu_reset_cbar_property = static Property arm_cpu_reset_hivecs_property = DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); -static Property arm_cpu_rvbar_property = - DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); - #ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property = DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); @@ -1240,7 +1240,9 @@ void arm_cpu_post_init(Object *obj) } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); + object_property_add_uint64_ptr(obj, "rvbar", + &cpu->rvbar_prop, + OBJ_PROP_FLAG_READWRITE); } #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 157f214..23879de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -447,6 +447,7 @@ typedef struct CPUArchState { uint64_t vbar_el[4]; }; uint32_t mvbar; /* (monitor) vector base address register */ + uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ struct { /* FCSE PID. */ uint32_t fcseidr_ns; uint32_t fcseidr_s; @@ -985,7 +986,7 @@ struct ArchCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; - uint64_t rvbar; + uint64_t rvbar_prop; /* Property/input signals. */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ int gic_num_lrs; /* number of list registers */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b5c8caa..812ca59 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7967,7 +7967,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8011,7 +8012,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar + .access = PL2_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8048,7 +8050,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo el3_regs[] = { { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, + .access = PL3_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, |