diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2018-07-31 11:14:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-31 11:14:53 +0100 |
| commit | 45a505d0a4b396a013ab086948a8ba6e76096bf4 (patch) | |
| tree | 127dd6c8700b2ed06eeca879901651cc57ea196e /target | |
| parent | fd76fef8e53e0f2876ef5f98e58b5c59fa1eb115 (diff) | |
| parent | cc4c77e12b422db8a685cec97866950895a684bc (diff) | |
| download | qemu-45a505d0a4b396a013ab086948a8ba6e76096bf4.zip qemu-45a505d0a4b396a013ab086948a8ba6e76096bf4.tar.gz qemu-45a505d0a4b396a013ab086948a8ba6e76096bf4.tar.bz2 | |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Bug fixes.
# gpg: Signature made Mon 30 Jul 2018 13:00:39 BST
# gpg: using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream:
backends/cryptodev: remove dead code
timer: remove replay clock probe in deadline calculation
i386: implement MSR_SMI_COUNT for TCG
i386: do not migrate MSR_SMI_COUNT on machine types <2.12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 | ||||
| -rw-r--r-- | target/i386/machine.c | 2 | ||||
| -rw-r--r-- | target/i386/misc_helper.c | 3 | ||||
| -rw-r--r-- | target/i386/smm_helper.c | 1 |
5 files changed, 8 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f454d4b..723e022 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5435,6 +5435,8 @@ static Property x86_cpu_properties[] = { false), DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), + DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, + true), /* * lecacy_cache defaults to true unless the CPU model provides its * own cache information (see x86_cpu_load_def()). diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 194e2e6..c18863e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1379,6 +1379,7 @@ struct X86CPU { bool expose_kvm; bool expose_tcg; bool migratable; + bool migrate_smi_count; bool max_features; /* Enable all supported features automatically */ uint32_t apic_id; diff --git a/target/i386/machine.c b/target/i386/machine.c index 8b64dff..084c2c7 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -400,7 +400,7 @@ static bool msr_smi_count_needed(void *opaque) X86CPU *cpu = opaque; CPUX86State *env = &cpu->env; - return env->msr_smi_count != 0; + return cpu->migrate_smi_count && env->msr_smi_count != 0; } static const VMStateDescription vmstate_msr_smi_count = { diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 628f64a..78f2020 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -447,6 +447,9 @@ void helper_rdmsr(CPUX86State *env) val = env->tsc_aux; break; #endif + case MSR_SMI_COUNT: + val = env->msr_smi_count; + break; case MSR_MTRRphysBase(0): case MSR_MTRRphysBase(1): case MSR_MTRRphysBase(2): diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c index 90621e5..c1c34a7 100644 --- a/target/i386/smm_helper.c +++ b/target/i386/smm_helper.c @@ -54,6 +54,7 @@ void do_smm_enter(X86CPU *cpu) qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); + env->msr_smi_count++; env->hflags |= HF_SMM_MASK; if (env->hflags2 & HF2_NMI_MASK) { env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; |