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author | Richard Henderson <richard.henderson@linaro.org> | 2018-03-02 10:45:41 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-02 11:03:45 +0000 |
commit | 449f264b1749ac0e59c58bbc2eacdb3dc302c2bf (patch) | |
tree | ef648eb909446d4c0dccb343a96605be44c2e087 /target | |
parent | 5f81b1de43259ed0969e62a7419ab9dd9da2c5c0 (diff) | |
download | qemu-449f264b1749ac0e59c58bbc2eacdb3dc302c2bf.zip qemu-449f264b1749ac0e59c58bbc2eacdb3dc302c2bf.tar.gz qemu-449f264b1749ac0e59c58bbc2eacdb3dc302c2bf.tar.bz2 |
target/arm: Refactor disas_simd_indexed size checks
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180228193125.20577-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/arm/translate-a64.c | 61 |
1 files changed, 30 insertions, 31 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fc928b6..cbb4510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11820,10 +11820,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x05: /* FMLS */ case 0x09: /* FMUL */ case 0x19: /* FMULX */ - if (size == 1) { - unallocated_encoding(s); - return; - } is_fp = true; break; default: @@ -11834,47 +11830,50 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) if (is_fp) { /* convert insn encoded size to TCGMemOp size */ switch (size) { - case 2: /* single precision */ - size = MO_32; - index = h << 1 | l; - rm |= (m << 4); - break; - case 3: /* double precision */ - size = MO_64; - if (l || !is_q) { + case 0: /* half-precision */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } - index = h; - rm |= (m << 4); - break; - case 0: /* half precision */ size = MO_16; - index = h << 2 | l << 1 | m; - is_fp16 = true; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { - break; - } - /* fallthru */ - default: /* unallocated */ + break; + case MO_32: /* single precision */ + case MO_64: /* double precision */ + break; + default: unallocated_encoding(s); return; } } else { switch (size) { - case 1: - index = h << 2 | l << 1 | m; - break; - case 2: - index = h << 1 | l; - rm |= (m << 4); - break; - default: + case MO_8: + case MO_64: unallocated_encoding(s); return; } } + /* Given TCGMemOp size, adjust register and indexing. */ + switch (size) { + case MO_16: + index = h << 2 | l << 1 | m; + break; + case MO_32: + index = h << 1 | l; + rm |= m << 4; + break; + case MO_64: + if (l || !is_q) { + unallocated_encoding(s); + return; + } + index = h; + rm |= m << 4; + break; + default: + g_assert_not_reached(); + } + if (!fp_access_check(s)) { return; } |