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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-12-17 18:06:21 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-02-27 22:29:01 +0100 |
| commit | 04bc30275876a4194233a763e1b8031f7a980813 (patch) | |
| tree | 0c5c173bf2a9b33f295fafeeeb8a57e2c013de8b /target | |
| parent | a1a65aade61fae15fdb6560e1a618865f6f21012 (diff) | |
| download | qemu-04bc30275876a4194233a763e1b8031f7a980813.zip qemu-04bc30275876a4194233a763e1b8031f7a980813.tar.gz qemu-04bc30275876a4194233a763e1b8031f7a980813.tar.bz2 | |
target/riscv/cpu: Move Floating-Point fields closer
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221217172907.8364-7-philmd@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d8e72c3..31537fc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -148,7 +148,6 @@ typedef struct PMUCTRState { struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ - uint64_t fpr[32]; /* assume both F and D extensions */ /* vector coprocessor state. */ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); @@ -163,7 +162,10 @@ struct CPUArchState { target_ulong load_res; target_ulong load_val; + /* Floating-Point state */ + uint64_t fpr[32]; /* assume both F and D extensions */ target_ulong frm; + float_status fp_status; target_ulong badaddr; target_ulong bins; @@ -379,8 +381,6 @@ struct CPUArchState { target_ulong cur_pmmask; target_ulong cur_pmbase; - float_status fp_status; - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |