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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-06-03 21:42:35 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:14 +1000 |
| commit | 03dd405dd5da6e0df3023bf9394ad0490b8369ab (patch) | |
| tree | 2f14130ceb01fe2791076d08f5692ca5e73d671d /target | |
| parent | 869d76f2073f6ed28e26bb264d4c2c8841f06496 (diff) | |
| download | qemu-03dd405dd5da6e0df3023bf9394ad0490b8369ab.zip qemu-03dd405dd5da6e0df3023bf9394ad0490b8369ab.tar.gz qemu-03dd405dd5da6e0df3023bf9394ad0490b8369ab.tar.bz2 | |
target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230603134236.15719-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/csr.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58499b5..6ac11d1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1311,11 +1311,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, } if (xl != MXL_RV32 || env->debugger) { - /* - * RV32: MPV and GVA are not in mstatus. The current plan is to - * add them to mstatush. For now, we just don't support it. - */ - mask |= MSTATUS_MPV | MSTATUS_GVA; + if (riscv_has_ext(env, RVH)) { + mask |= MSTATUS_MPV | MSTATUS_GVA; + } if ((val & MSTATUS64_UXL) != 0) { mask |= MSTATUS64_UXL; } @@ -1351,7 +1349,7 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, target_ulong val) { uint64_t valh = (uint64_t)val << 32; - uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; + uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; env->mstatus = (env->mstatus & ~mask) | (valh & mask); |