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authorRichard Henderson <richard.henderson@linaro.org>2023-02-15 19:45:15 -1000
committerLaurent Vivier <laurent@vivier.eu>2023-03-10 20:45:47 +0100
commit4ea3af392f85dc2e66059855266b3817b321dc90 (patch)
treeb5ecde2626d54ae6e503d38be4779060d5f02b0c /target/sparc
parent81f04cd34ccd3dab6c796a5fbc439a8061b04ef3 (diff)
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linux-user/sparc: Handle floating-point exceptions
Raise SIGFPE for ieee exceptions. The other types, such as FSR_FTT_UNIMPFPOP, should not appear, because we enable normal emulation of missing insns at the start of sparc_cpu_realizefn(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target/sparc')
-rw-r--r--target/sparc/cpu.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index ed0069d..fb98843 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -197,8 +197,7 @@ enum {
#define FSR_FTT2 (1ULL << 16)
#define FSR_FTT1 (1ULL << 15)
#define FSR_FTT0 (1ULL << 14)
-//gcc warns about constant overflow for ~FSR_FTT_MASK
-//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#ifdef TARGET_SPARC64
#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL