diff options
author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:41 +0530 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:18 +1000 |
commit | f87adf23fa66fd07d9f003173d386c0a54d9ddb0 (patch) | |
tree | 26b2a4c7a883a6583fb3f434aad388885691ffb0 /target/riscv | |
parent | 02d9565b92c97af6bac2ff1bb18967a5e95b9694 (diff) | |
download | qemu-f87adf23fa66fd07d9f003173d386c0a54d9ddb0.zip qemu-f87adf23fa66fd07d9f003173d386c0a54d9ddb0.tar.gz qemu-f87adf23fa66fd07d9f003173d386c0a54d9ddb0.tar.bz2 |
target/riscv: Allow setting CPU feature from machine/device emulation
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/cpu.c | 11 | ||||
-rw-r--r-- | target/riscv/cpu.h | 5 |
2 files changed, 8 insertions, 8 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f1c2684..ff766ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -135,11 +135,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY @@ -508,18 +503,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); + riscv_set_feature(env, RISCV_FEATURE_MMU); } if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); + riscv_set_feature(env, RISCV_FEATURE_PMP); /* * Enhanced PMP should only be available * on harts with PMP support */ if (cpu->cfg.epmp) { - set_feature(env, RISCV_FEATURE_EPMP); + riscv_set_feature(env, RISCV_FEATURE_EPMP); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f030cb5..283a3cd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -379,6 +379,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) return env->features & (1ULL << feature); } +static inline void riscv_set_feature(CPURISCVState *env, int feature) +{ + env->features |= (1ULL << feature); +} + #include "cpu_user.h" extern const char * const riscv_int_regnames[]; |