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-rw-r--r--target/riscv/cpu.c11
-rw-r--r--target/riscv/cpu.h5
2 files changed, 8 insertions, 8 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f1c2684..ff766ac 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,11 +135,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
env->vext_ver = vext_ver;
}
-static void set_feature(CPURISCVState *env, int feature)
-{
- env->features |= (1ULL << feature);
-}
-
static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
@@ -508,18 +503,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.mmu) {
- set_feature(env, RISCV_FEATURE_MMU);
+ riscv_set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
- set_feature(env, RISCV_FEATURE_PMP);
+ riscv_set_feature(env, RISCV_FEATURE_PMP);
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
if (cpu->cfg.epmp) {
- set_feature(env, RISCV_FEATURE_EPMP);
+ riscv_set_feature(env, RISCV_FEATURE_EPMP);
}
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f030cb5..283a3cd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -379,6 +379,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
return env->features & (1ULL << feature);
}
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+ env->features |= (1ULL << feature);
+}
+
#include "cpu_user.h"
extern const char * const riscv_int_regnames[];