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| author | Bin Meng <bmeng@tinylab.org> | 2023-02-28 21:45:30 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 16:40:21 -0800 |
| commit | fb517fdb150b71d6fad8e2332c9aace82143e45f (patch) | |
| tree | 637c87d7b3b6d9e2d54bcf769f3ad74246a17eb1 /target/riscv/monitor.c | |
| parent | 7eac8f4191561492fa9fa1e12c80fe27d9842fc6 (diff) | |
| download | qemu-fb517fdb150b71d6fad8e2332c9aace82143e45f.zip qemu-fb517fdb150b71d6fad8e2332c9aace82143e45f.tar.gz qemu-fb517fdb150b71d6fad8e2332c9aace82143e45f.tar.bz2 | |
target/riscv: Allow debugger to access user timer and counter CSRs
At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.
Fix it by adding a debugger check in their predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-14-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/monitor.c')
0 files changed, 0 insertions, 0 deletions