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| author | Michael Clark <mjc@sifive.com> | 2019-03-16 01:21:12 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:14:40 -0700 |
| commit | 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7 (patch) | |
| tree | 3befad4f4f5aebdc43c661520c5b330b67bc9533 /target/riscv/csr.c | |
| parent | acbbb94e5730c9808830938e869d243014e2923a (diff) | |
| download | qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.zip qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.tar.gz qemu-929f0a7fc40d7123ddda4c9dbd78a1806999b4f7.tar.bz2 | |
RISC-V: Convert trap debugging to trace events
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/csr.c')
0 files changed, 0 insertions, 0 deletions