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| author | Anup Patel <apatel@ventanamicro.com> | 2022-11-08 18:26:59 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | 6535a443345d659882444f0db1fafd22ba1f803a (patch) | |
| tree | 97974901476d3fb8db6ed0171f3066e978019071 /target/riscv/csr.c | |
| parent | 0a9a6cba8b9cad8786670fd8c9fa1b0d39bd00e8 (diff) | |
| download | qemu-6535a443345d659882444f0db1fafd22ba1f803a.zip qemu-6535a443345d659882444f0db1fafd22ba1f803a.tar.gz qemu-6535a443345d659882444f0db1fafd22ba1f803a.tar.bz2 | |
target/riscv: Typo fix in sstc() predicate
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 71236f2..0db2c23 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -940,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) } if (riscv_cpu_virt_enabled(env)) { - if (!(get_field(env->hcounteren, COUNTEREN_TM) & + if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } |