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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:26:54 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:24 -0700 |
| commit | 0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc (patch) | |
| tree | b68ccceb76bda361e2dfedec4fe55fe34040acbe /target/riscv/csr.c | |
| parent | 356d74192a035c71a78a22d24812a6df6099ae40 (diff) | |
| download | qemu-0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc.zip qemu-0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc.tar.gz qemu-0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc.tar.bz2 | |
target/riscv: Trigger interrupt on MIP update asynchronously
The requirement of holding the iothread_mutex is burdersome when
swapping the background and foreground registers in the Hypervisor
extension. To avoid the requrirement let's set the interrupt
asynchronously.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e1d91b6..f9d8d15 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -555,9 +555,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, uint32_t old_mip; if (mask) { - qemu_mutex_lock_iothread(); old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); - qemu_mutex_unlock_iothread(); } else { old_mip = atomic_read(&env->mip); } |