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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:52 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | f714361ed79180a9780334cfe1b89b69f6c9bfe9 (patch) | |
| tree | 424f1a7e60e908d60d3ed2083601dedfb3d1cd67 /target/riscv/cpu.c | |
| parent | 8a4b52575ab1793f5cc86ddd0b5e986799dfc615 (diff) | |
| download | qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.zip qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.tar.gz qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.tar.bz2 | |
target/riscv: rvv-1.0: implement vstart CSR
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first loads) to raise the memory access exception
at the exact processed vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
0 files changed, 0 insertions, 0 deletions