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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-02-20 10:56:12 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 16:59:50 -0800 |
| commit | b7fa70e2afa6c784f21f749572ce78f6467666fd (patch) | |
| tree | 1249ce7c9ad96c60fe98cb434c0754444e2d2ffe /target/riscv/cpu.c | |
| parent | ae9c326fb6f9b580b18de9bce1438229bfaa5215 (diff) | |
| download | qemu-b7fa70e2afa6c784f21f749572ce78f6467666fd.zip qemu-b7fa70e2afa6c784f21f749572ce78f6467666fd.tar.gz qemu-b7fa70e2afa6c784f21f749572ce78f6467666fd.tar.bz2 | |
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230220095612.1529031-1-christoph.muellner@vrull.eu>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/cpu.c')
0 files changed, 0 insertions, 0 deletions