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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:14:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 13514fc93e6b2ead6e984bcd104975b6b4f375e8 (patch) | |
| tree | 0a1ea93a3afe95fdc91cdf4ae10ad69e5d3526f3 /target/mips/translate.c | |
| parent | d913c3992dfd9506a8201c2995d7c910a18db92f (diff) | |
| download | qemu-13514fc93e6b2ead6e984bcd104975b6b4f375e8.zip qemu-13514fc93e6b2ead6e984bcd104975b6b4f375e8.tar.gz qemu-13514fc93e6b2ead6e984bcd104975b6b4f375e8.tar.bz2 | |
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 9fc9ded..fc93b9d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, |