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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-09 18:42:46 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 20b28ebc49945583d7191b57755cfd92433de9ff (patch) | |
| tree | 6b208ad43fab225372cacefb1def8f370b390252 /target/mips/helper.h | |
| parent | fa75ad1459f4f6abbeb6d375a812dfad61320f58 (diff) | |
| download | qemu-20b28ebc49945583d7191b57755cfd92433de9ff.zip qemu-20b28ebc49945583d7191b57755cfd92433de9ff.tar.gz qemu-20b28ebc49945583d7191b57755cfd92433de9ff.tar.bz2 | |
target/mips: Add CP0 PWSize register
Add PWSize register (CP0 Register 5, Select 7).
The PWSize register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
BDW (37..32) Base Directory index width (MIPS64 only)
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/helper.h')
| -rw-r--r-- | target/mips/helper.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/helper.h b/target/mips/helper.h index 6366f9b..169890a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl) DEF_HELPER_2(mtc0_segctl1, void, env, tl) DEF_HELPER_2(mtc0_segctl2, void, env, tl) DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) DEF_HELPER_2(mtc0_wired, void, env, tl) DEF_HELPER_2(mtc0_srsconf0, void, env, tl) DEF_HELPER_2(mtc0_srsconf1, void, env, tl) |