From 20b28ebc49945583d7191b57755cfd92433de9ff Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Tue, 9 Oct 2018 18:42:46 +0200 Subject: target/mips: Add CP0 PWSize register Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/mips/helper.h') diff --git a/target/mips/helper.h b/target/mips/helper.h index 6366f9b..169890a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl) DEF_HELPER_2(mtc0_segctl1, void, env, tl) DEF_HELPER_2(mtc0_segctl2, void, env, tl) DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) DEF_HELPER_2(mtc0_wired, void, env, tl) DEF_HELPER_2(mtc0_srsconf0, void, env, tl) DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -- cgit v1.1