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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-07-04 13:05:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-07-04 13:05:30 +0100 |
| commit | 2185c93ba80f81bfa27ce6f259c7f2ef4f08b668 (patch) | |
| tree | f2bfba6f066e0f5da675ad95bf1cb2df4921a5c0 /target/microblaze/cpu.c | |
| parent | 0c7a8b9baa744ae4323bb46cb4fe942355beaa85 (diff) | |
| parent | 31cf950ea2a010c33e5384aaba91f01dc27c1599 (diff) | |
| download | qemu-2185c93ba80f81bfa27ce6f259c7f2ef4f08b668.zip qemu-2185c93ba80f81bfa27ce6f259c7f2ef4f08b668.tar.gz qemu-2185c93ba80f81bfa27ce6f259c7f2ef4f08b668.tar.bz2 | |
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next.for-upstream' into staging
edgar/xilinx-next.for-upstream
# gpg: Signature made Tue 04 Jul 2017 10:00:47 BST
# gpg: using RSA key 0x29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83
* remotes/edgar/tags/edgar/xilinx-next.for-upstream:
xilinx-dp: Add support for the yuy2 video format
target-microblaze: Add CPU version 10.0
target-microblaze: dec_barrel: Add BSIFI
target-microblaze: dec_barrel: Add BSEFI
target-microblaze: dec_barrel: Plug TCG temp leak
target-microblaze: dec_barrel: Add braces around if-statements
target-microblaze: dec_barrel: Use extract32
target-microblaze: dec_barrel: Use bool instead of unsigned int
target-microblaze: Introduce a use-pcmp-instr property
target-microblaze: Introduce a use-msr-instr property
target-microblaze: Introduce a use-hw-mul property
target-microblaze: Introduce a use-div property
target-microblaze: Introduce a use-barrel property
target-microblaze: Add CPU versions 9.4, 9.5 and 9.6
target-microblaze: Don't hard code 0xb as initial MB version
target-microblaze: Correct bit shift for the PVR0 version field
disas/microblaze: Add missing 'const' attributes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/microblaze/cpu.c')
| -rw-r--r-- | target/microblaze/cpu.c | 39 |
1 files changed, 25 insertions, 14 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 3d58869..f85ff01 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -64,6 +64,10 @@ static const struct { {"9.1", 0x1D}, {"9.2", 0x1F}, {"9.3", 0x20}, + {"9.4", 0x21}, + {"9.5", 0x22}, + {"9.6", 0x23}, + {"10.0", 0x24}, {NULL, 0}, }; @@ -147,23 +151,13 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ - | PVR0_USE_DIV_MASK \ - | PVR0_USE_HW_MUL_MASK \ - | PVR0_USE_EXC_MASK \ + env->pvr.regs[0] = PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | (0xb << 8); + | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ - | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_BARREL_MASK \ - | PVR2_USE_DIV_MASK \ - | PVR2_USE_HW_MUL_MASK \ - | PVR2_USE_MUL64_MASK \ | PVR2_FPU_EXC_MASK \ | 0; @@ -180,13 +174,22 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << 16) | + (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | - (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -233,6 +236,14 @@ static Property mb_properties[] = { * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), + /* If use-hw-mul > 0 - Multiplier is enabled + * If use-hw-mul = 2 - 64-bit multiplier is enabled + */ + DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), + DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), + DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), + DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), + DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), |