From 79549c996056ce1ad820061622e71d4a0444d3c7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 10 Jan 2017 17:14:34 +0100 Subject: target-microblaze: Correct bit shift for the PVR0 version field Correct bit shift for the PVR0 version field. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 3d58869..af70faa 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -182,7 +182,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << 16) | + (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | -- cgit v1.1 From 3e92250589c617b8cff74cbe6641ba2459717a27 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 10 Jan 2017 17:24:01 +0100 Subject: target-microblaze: Don't hard code 0xb as initial MB version Don't hard code 0xb as initial MB version. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index af70faa..4bc77df 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -152,8 +152,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | (0xb << 8); + | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ -- cgit v1.1 From d79fcbc298b06f8e2bb37aecd23f22b1b9972d31 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Wed, 11 Jan 2017 12:06:52 +0100 Subject: target-microblaze: Add CPU versions 9.4, 9.5 and 9.6 Add CPU versions 9.4, 9.5 and 9.6. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4bc77df..982cb61 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -64,6 +64,9 @@ static const struct { {"9.1", 0x1D}, {"9.2", 0x1F}, {"9.3", 0x20}, + {"9.4", 0x21}, + {"9.5", 0x22}, + {"9.6", 0x23}, {NULL, 0}, }; -- cgit v1.1 From 7faa66aaf88fd0acc35c86bf56d688eeeee841c7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Fri, 16 Jun 2017 17:21:05 +0200 Subject: target-microblaze: Introduce a use-barrel property Introduce a use-barrel property making barrel shifter instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 982cb61..bae47b5 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ - | PVR0_USE_DIV_MASK \ + env->pvr.regs[0] = PVR0_USE_DIV_MASK \ | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ @@ -162,7 +161,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_BARREL_MASK \ | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ @@ -182,13 +180,15 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | - (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -235,6 +235,7 @@ static Property mb_properties[] = { * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), + DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), -- cgit v1.1 From 47709e4c66239819cfe2e965e6aa30b646c09ad6 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sun, 18 Jun 2017 09:34:36 +0200 Subject: target-microblaze: Introduce a use-div property Introduce a use-div property making division instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bae47b5..5bf2a29 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_DIV_MASK \ - | PVR0_USE_HW_MUL_MASK \ + env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ | PVR0_USE_DCACHE_MASK; @@ -161,7 +160,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ | PVR2_FPU_EXC_MASK \ @@ -181,6 +179,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | - (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0); + (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -236,6 +236,7 @@ static Property mb_properties[] = { */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), + DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), -- cgit v1.1 From 9b9643181a2324f4ecefd39367fd83be2ba837d6 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:06:44 +0200 Subject: target-microblaze: Introduce a use-hw-mul property Introduce a use-div property making multiplication instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5bf2a29..70e4743 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \ - | PVR0_USE_EXC_MASK \ + env->pvr.regs[0] = PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ @@ -160,8 +159,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_I_LMB_MASK \ | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_HW_MUL_MASK \ - | PVR2_USE_MUL64_MASK \ | PVR2_FPU_EXC_MASK \ | 0; @@ -178,6 +175,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | @@ -187,6 +185,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | + (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | + (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); @@ -235,6 +235,10 @@ static Property mb_properties[] = { * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), + /* If use-hw-mul > 0 - Multiplier is enabled + * If use-hw-mul = 2 - 64-bit multiplier is enabled + */ + DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), -- cgit v1.1 From 5683750909fb407261b5ad00fed4ad9460ab6845 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:13:26 +0200 Subject: target-microblaze: Introduce a use-msr-instr property Introduce a use-msr-instr property making msr instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 70e4743..bc96505 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ | PVR2_FPU_EXC_MASK \ | 0; @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -241,6 +241,7 @@ static Property mb_properties[] = { DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), + DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), -- cgit v1.1 From 8fc5239e1f8df617147dfe9761dd78291fea78d7 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 20 Jun 2017 13:53:53 +0200 Subject: target-microblaze: Introduce a use-pcmp-instr property Introduce a use-pcmp-instr property making pcmp instructions optional. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bc96505..6e27c3c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_PCMP_INSTR \ | PVR2_FPU_EXC_MASK \ | 0; @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | - (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -242,6 +242,7 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), + DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), -- cgit v1.1 From feac83af3be68ac8f7325dd7f9c851272a9f217e Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 15 Jun 2017 13:37:10 +0200 Subject: target-microblaze: Add CPU version 10.0 Add CPU version 10.0. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target/microblaze/cpu.c') diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6e27c3c..f85ff01 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -67,6 +67,7 @@ static const struct { {"9.4", 0x21}, {"9.5", 0x22}, {"9.6", 0x23}, + {"10.0", 0x24}, {NULL, 0}, }; -- cgit v1.1