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authorPeter Maydell <peter.maydell@linaro.org>2024-12-11 15:30:55 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-12-11 15:30:55 +0000
commit390df9046b58249dfac2590a914422834c8333c6 (patch)
tree4dcba0dc0ead31720baa08cc2f585b435aac1a68 /target/i386
parent67c0df045ec11da24bd2f18f81813ed9ff48b4c5 (diff)
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target/x86: Set FloatInfZeroNaNRule explicitly
Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
Diffstat (limited to 'target/i386')
-rw-r--r--target/i386/tcg/fpu_helper.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 53b49bb..3295753 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env)
*/
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
+ /*
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
+ * there are multiple input NaNs they are selected in the order a, b, c.
+ */
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
}
static inline uint8_t save_exception_flags(CPUX86State *env)