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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:55 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:55 +0000 |
| commit | 390df9046b58249dfac2590a914422834c8333c6 (patch) | |
| tree | 4dcba0dc0ead31720baa08cc2f585b435aac1a68 | |
| parent | 67c0df045ec11da24bd2f18f81813ed9ff48b4c5 (diff) | |
| download | qemu-390df9046b58249dfac2590a914422834c8333c6.zip qemu-390df9046b58249dfac2590a914422834c8333c6.tar.gz qemu-390df9046b58249dfac2590a914422834c8333c6.tar.bz2 | |
target/x86: Set FloatInfZeroNaNRule explicitly
Set the FloatInfZeroNaNRule explicitly for the x86 target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
| -rw-r--r-- | fpu/softfloat-specialize.c.inc | 2 | ||||
| -rw-r--r-- | target/i386/tcg/fpu_helper.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19..ad4f709 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb..3295753 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is + * specified -- for 0 * inf + NaN the input NaN is selected, and if + * there are multiple input NaNs they are selected in the order a, b, c. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) |