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| author | Paolo Bonzini <pbonzini@redhat.com> | 2019-10-16 10:34:39 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-10-26 15:38:07 +0200 |
| commit | bf13bfab0840d34a74938ddf567d52e9010dbdc6 (patch) | |
| tree | 2743c5d7e769c7da29ddc7fcdb795a869514668e /target/i386/cpu.h | |
| parent | 5caa1833d22c2f3c3f08c80d9bf86dccf9aa25a4 (diff) | |
| download | qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.zip qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.tar.gz qemu-bf13bfab0840d34a74938ddf567d52e9010dbdc6.tar.bz2 | |
i386: implement IGNNE
Change the handling of port F0h writes and FPU exceptions to implement IGNNE.
The implementation mixes a bit what the chipset and processor do in real
hardware, but the effect is the same as what happens with actual FERR#
and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering
FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 01e052b..5352c9f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -203,6 +203,7 @@ typedef enum X86Seg { #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ +#define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) @@ -211,6 +212,7 @@ typedef enum X86Seg { #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) +#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) #define CR0_PE_SHIFT 0 #define CR0_MP_SHIFT 1 @@ -1762,7 +1764,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); int cpu_get_pic_interrupt(CPUX86State *s); /* MSDOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); -void cpu_clear_ferr(void); +void cpu_set_ignne(void); /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); |