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| author | Paolo Bonzini <pbonzini@redhat.com> | 2023-02-27 10:55:46 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-02-27 18:44:03 +0100 |
| commit | 58794f644e43ef8e60ed05395c58099311c1fcd1 (patch) | |
| tree | 1b1a2a29036c292c90b634ed281dd58f698196ed /target/i386/cpu.h | |
| parent | c0728d4e3d23356691e4182eac54c67e1ca26618 (diff) | |
| download | qemu-58794f644e43ef8e60ed05395c58099311c1fcd1.zip qemu-58794f644e43ef8e60ed05395c58099311c1fcd1.tar.gz qemu-58794f644e43ef8e60ed05395c58099311c1fcd1.tar.bz2 | |
target/i386: add FZRM, FSRS, FSRC
These are three more markers for string operation optimizations.
They can all be added to TCG, whose string operations are more or
less as fast as they can be for short lengths.
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc195..e0703fe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -900,6 +900,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* Fast Zero REP MOVS */ +#define CPUID_7_1_EAX_FZRM (1U << 10) +/* Fast Short REP STOS */ +#define CPUID_7_1_EAX_FSRS (1U << 11) +/* Fast Short REP CMPS/SCAS */ +#define CPUID_7_1_EAX_FSRC (1U << 12) + /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) |